Lower Power Synthesis - VADA

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Transcript Lower Power Synthesis - VADA

L35: Lower Power Voltage
Scaling
1999. 8.
성균관대학교 조 준 동
http://vada.skku.ac.kr
SungKyunKwan Univ.
VADA Lab.
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Voltage Scaling
• Merely changing a processor clock frequency
is not an effective technique for reducing
energy consumption. Reducing the clock
frequency will reduce the power consumed by
a processor, however, it does not reduce the
energy required to perform a given task.
• Lowering the voltage along with the clock
actually alters the energy-per-operation of the
microprocessor, reducing the energy required
to perform a fixed amount of work.
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Dynamic Voltage Scaling(DVS)
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Processor Usage Model
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OS: Voltage Scaling
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Scale Supply Voltage with
fCLK
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Adaptive Power Supply
Voltages
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Variable Supply Voltage Block Diagram
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Typical MPEG IDCT
Histogram
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Voltage scheduling under timing constraints
– Energy consumption of a processor:
• 10nJ/cycle at 2.5V
• 25nJ/cycle at 4 V
• 40nJ/cycle at 5V
– maximum clock frequencies:
• 50MHz at 5V, 40MHz at 4V, 25MHz at 2.5V
– Given that an application needs 1000M cycles
to finish and the timing constaint is 25sec.
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Energy consumption ( Vdd2)
Different Voltage Schedules
40J
1000Mcycles
50MHz
5.02
0
5.02
5
10
15
32.5J
750Mcycles
50MHz
Timing constraint
(A)
20
25
250Mcycles
25MHz
Time(sec)
(B)
2.52
0
5
5.02
4.02
10
15
20
25
25J
1000Mcycles
40MHz
0
5
10
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Time(sec)
(C)
20
25
Time(sec)
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Example of Variable Supply
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DVS Implementation
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Variable Supply Voltage Block Diagram
•
•
•
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Computational work varies with
time. An approach to reduce
the energy consumption of
such systems beyond shut
down involves the dynamic
adjustment of supply voltage
based on computational
workload.
The basic idea is to lower
power supply when the a fixed
supply for some fraction of
time.
The supply voltage and clock
rate are increased during high
workload period.
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Data Driven Signal Processing
The basic idea of
averaging two samples
are buffered and their
work loads are
averaged.
The averaged workload
is then used as the
effective workload to
drive the power supply.
Using a pingpong
buffering scheme, data
samples In +2, In +3
are being buffered while
In, In +1
are being processed.
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Example of Buffering
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Graphical Interpretation
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Buffering Example: MPEG Decoder
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DVS
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DVS Scheduling Framework
Energy ~ Work • Speed
µProc. Speed
Start
Work
Deadline
Idle time
represents
wasted
energy
Start
Deadline
Lower speed,
Lower voltage,
Lower energy
Work
Time
• Use real-time framework to
constrain task voltage scheduling
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DVS Simulation
Interrupts
S2
S3 D1
D3
D2
Task
Variance
Speed
S1
Time
Theory
User
Input
Cache
Behavior
Scheduling
Overhead
Intercom
Weather
Reality
Implementation
Simulate run-time scheduler to
fully understand voltage-scaling behavior
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Simulation Infrastructure
GUI
MPEG
{
Frame_Start(deadline);
Decode_MPEG_Frame();
Frame_Finish();
Cryptography
}
Windowing
I/O Support
Application
support libraries
Voltage
Scheduler
MPEG  Priority 80
GUI  Priority 23
Run-time
Scheduler Speed  Priority
lpARM
Develop support environment to
model complete software system
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Normalized
to 3.3V
fixed-voltage
processor
Total System Energy
Run-Time Voltage Scaling
100%
80%
DVS Simulation
Post-Trace Optimal
73%
65%
58%
60%
46%
40%
20%
16% 15%
25% 20%
Combination
of independent
benchmarks
0%
Audio
GUI
MPEG
Audio &
MPEG
• Dynamic Voltage Scaling
significantly reduces energy dissipation!
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Run-Time Performance Analysis
80%
60%
Audio
GUI
MPEG
40%
20%
0%
0 Fixed-V Frame Execution Time 2x
deadline
Normalized to
deadline at max
processor speed
100%
Total System Energy
100%
Frame Computation Histogram
80%
DVS System Energy
Basic Algorithm
Adjusted Algorithm
Post-Trace Optimal
60%
40%
20%
0%
Audio
MPEG
GUI
Software can automatically
recognize and adjust for
bi-modal GUI distribution
• Application characteristics strongly affect
voltage scaling performance
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Compute ASAP+ System
Shutdown
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Another Approach: Reduce Clock
Frequency
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Voltage Scheduling II
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Evaluation: Algorithms
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AVG<weight>
• Computes an exponentially moving average of the
previous intervals. At each interval the run-percent
from the previous interval is combined with the
previous running average, forming a long-term
prediction of system behavior. <weight> is the
relative weighting of past intervals relative of the
current interval (larger value means a great weight
on the past) using the equation (weight X old +
new)/(weight+1). 3 can be used.
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OS: Voltage Scheduling
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Run-Time Scheduling Dynamics
µProc. Speed
Run faster
to make up
lost time
Thread accomplishing
more than expected,
reduce speed
Deadline exceeded,
increase speed
Higher-priority
task
Initial speed
estimate
Time
E(work)
Optimal
schedule
Workload calculated to be
average of previous frames
• Periodically re-evaluate schedule to
adjust for unforeseen events
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Vertical Layering
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Optimal Scheduling
• For a region spanned by a given task
specification, each point in time will either be
scheduled at the minimum speed spanned by
that task or else the task will not be
scheduled to run at that point.
Algorithm
• n tasks to schedule
• O(n) speed settings to consider for each task
• O(n) linked tasks requiring adjustment for
each setting: Total complexity: O(n 3 ) time.
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Scheduling step0
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Scheduling step1
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Scheduling step2
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Scheduling step3
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Scheduling step4
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Scheduling step5
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References
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