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Deep Submicron Design 1998. 5. 19 조준동 SungKyunKwan Univ. VADA Lab. 1 SungKyunKwan Univ. VADA Lab. 2 Deep Submicron Problem • • • • As physical feature sizes decrease, the time delay of electrical signals traveling in the interconnect between active devices and gates is approaching the delay through the devices and gates. Therefore, the parasitic information (resistance and capacitance) of the interconnect is absolutely critical to predicting circuit performance. The key to solving this problem is knowing more about the physical design, i.e. placement and estimated interconnect, early in the design cycle. Iterations between synthesis and layout increase dramatically due to timing and routability problems. The RTL is being defined to accurately predict size, timing and power, early in the design cycle and avoid downstream iterations. It should also include constraint capture for defining, managing, and budgeting design constraints. SungKyunKwan Univ. VADA Lab. 3 Difficulty in Deep Submicron SungKyunKwan Univ. VADA Lab. 4 Deep Submicron Technology • • • • Although there is no official line for what constitutes a deep submicron, the term generally refers to a CMOS device whose minimum logic gate length is 0.5 um or smaller. Deep submicron technology gives the chip manufacturers' ability to put more gates in chips and increase the density of chips. These make chips more powerful and smaller. Most current VLSI tools could not handle the new problems, such as accurate RC extraction, transmission line effect and coupling effect, raised by deep submicron technology properly. Even models for VLSI ASIC designs, such as timing delays, routability, size and power dissipation will need to be modified or to be improved. In non-submicron integrated circuits that do not require high clock operation speed, minimum-width line can be used for clock distribution. Since the difference of logic gate delays in the signal paths dominates the clock skew, wire length does not affect the clock skew much. The interconnect wire delay is not a big issue. Under these conditions, the rule of thumb is to use the same number of identical buffers for each signal path, such that every component will experience the same logic gate delay. However, in high speed VLSI design using submicron or deep submicron technology, the clock skew is not only affected by the logic gate delay, but also by the distance between logic gates. The clock skew can be minimized by distributing the clock signal in such a fashion that the wire load, which consists of logic gate input capacitance, logic gate output capacitance, logic gate delay, wire resistance and wire capacitance, of the functional sub-blocks are equal. Clearly the traditional method, mentioned in the last paragraph, is not feasible any more. When designers estimate the clock skew, they need to include the logic gate delay and interconnect wire delay in the estimation. SungKyunKwan Univ. VADA Lab. 5 Deep Submicron Constraints • The assumptions made at the beginning are valid. However, the assumptions are not very practical. Since in most designs different wire width and different metal layers are used, the clock tree distribution algorithms need to be adjusted accordingly. Although interconnect wire delay becomes more important than the logic gate delay, the need to have correct models for both wire delay and logic gate delay is urgent and necessary. • Simple linear logic gate modeling is no longer accurate enough. Look up table and piece-wise interpolating are needed to provide more accurate logic gate delay estimation. Correct and detailed circuit simulation of the logic gate characteristics should be employed; however, this consumes a lot of computing power. • Interconnect wire modeling is also not linear anymore. Correct RC extraction and circuit extraction are necessary for accurate simulation results. For example, a wire passing under or over other wires has different capacitance with another wire with nothing above or below. Via holes can also contribute small changes in the interconnect wire resistance and wire capacitance. SungKyunKwan Univ. VADA Lab. 6 Deep Submicron Constraints • • • • • Together, high-performance architecture and circuits trends, time to market, and the economics of system-on-chip integration imply that in 2001: Nearly all 60+ million non-memory transistors will be in pre-designed blocks; 30-95% of them will be in wide data paths, with top-level interconnect dominated by wide buses; A significant fraction of the design will have an "analog" or mixed-signal flavor. Constraints on routing will include: – High-level system timing and boundary conditions; – Detailed budgeted slacks and required arrival times; – Thermal, hot-electron and electromigration reliability rules; – Noise margins at various classes of logic nodes. SungKyunKwan Univ. VADA Lab. 7 Benefits and Risks Impact on Submicron design • Data Explosion: Device counts are reaching tens of millions, creating a data explosion in the physical design database. • Interconnect Dominates Performance: Chip performance is now strongly determined by the parasitic effects of the passive structures interconnecting active devices. Deep Submicron Benefits • Increased functionality--more transistors residing on a die result in each chip containing increased functionality. • Cost Reduction--a significant reduction in costs can be realized because the same number of transistors on a smaller chip result in more die per wafer. • Faster Designs--smaller transistors switch faster, enabling designs to run faster. Deep Submicron Manufacturing Risks: • Time to Market--current tools cannot keep pace with silicon manufacturing capabilities due to the huge device-count Deep Submicron designs. Reliability--a substantial increase in the density of designs (data volume and device proximity). Increased failure rates are a becoming a substantial constributor to manufacturing costs. Performance-each new project requires a new methodology to account for the impact of interconnect on overall system performance. SungKyunKwan Univ. VADA Lab. 8 Technology Advancements • • • • • • • • • • • • One of the ramifications of deep submicron is sub-nanosecond gate delays. SEMATECH and others say forget 200 MHz clock rate. The future is 300 MHz to 600 MHz clock rate. Three Hundred MHz equal 3.3 nanoseconds clock period. Pipeline architecture with 10 levels of logic means a maximum gate delay of 330 picoseconds. Unfortunately, there is interconnect between gates. Interconnect delay will equal or be greater than the gate delay. This means maximum gate delay will be about 165 picoseconds. INTERCONNECT DELAY DOMINATES. Tighter pitch means sidewall capacitance increases Height-to-width ratio is expected to increase from 1.5 today to 2.5 in the future Sidewall Capacitance dominates; it is the laws of physics Crosstalk becomes an issue High gain analog most susceptible RAM circuitry is also sensitive Portable small signal swing digital applications SungKyunKwan Univ. VADA Lab. 9 Technology Advancement Systems on a Chip • Another term is "Systems on Silicon," referring to chips with 10 million or more transistors (many chips are already at 3 to 7 million). Ten million-plus extrapolates to 2 million-plus equivalent gates, which in turn implies one quarter million-plus nets, excluding power and ground. This also ignores the fact physical nets have multiple branches. • Conclusion: thousands to tens of thousands of nets may need to be analyzed or screened. Other Advancements in Technology • Advancements in technology besides deep submicron are creating challenges for design engineers. Analog mixed signal is a very fast-growing market. It has been growing at a compound annual growth rate of 20 percent to 30 percent vs. the overall IC chip sales of 10 percent to 12 percent. Today's volumes of IC chip sales have far exceeded these numbers. Analog mixed signal designs require the merging of analog (linear) circuitry and digital logic circuitry on the same chip. In many cases embedded RAM is required. Digital circuitry generates a great deal of noise. Unfortunately, analog circuits and RAM circuits are very noise sensitive, so noise isolation and noise coupling are a very important consideration in the design of these chips. Noise is coupled through the interconnect making accurate modeling of the interconnect parasitics is an important requirement. • The design engineer needs a good understanding of parasitic capacitance sensitivity to physical layout and process parameters. This means the design engineer needs to get back to the fundamentals of physics. SungKyunKwan Univ. VADA Lab. 10 Design Systems of Today • The two key knowledge reservoirs of today's design systems are the technology library and cell library. The Technology Library contains the technology information that needs to be imparted to the tools in the design system. – Simulation models; device, gate level and behavioral. – Design rules; physical and timing. • The Cell Library is essentially the design database. – – – – Symbols. Schematics. Physical cells from primitives to large functional cores. Simulation results. SungKyunKwan Univ. VADA Lab. 11 Advanced routing for deep submicron technologies • Smaller feature sizes, higher clock speeds, and lower supply voltages in 2001 will call for a new IC routing technology. Leading-edge CMOS processes will be at 0.12-micron minimum feature size, with 0.9-V supply voltage. Dies will be severely interconnectlimited, despite back-side power distribution (distributing power via plated throughholes or other means). Local interconnects (wires on metal layers 1-4) will have aspect ratios as high as 3:1, with minimum contacted pitch of 0.35 micron meter. A short 100micron meter local metal trace will have over 80 ohm resistance and 20 fF capacitance. And, 5 micron meter of wire will give the same capacitive load as a gate input. At the same time, minimum inverter delays will approach 40 ps, and global interconnects (on metal layer 5-10) will be carefully pre-routed and/or assigned to layers, since the layers will be highly tuned to enable balancing of signal performance, signal distribution, and clock/power distribution. With ten layers of interconnect, layouts will be virtually channelless. A leading-edge design will also have 120 million transistors connected by over 4 km of wire, in a die 20,000 micron meter on a side. Clock frequency will be well over 1 Ghz. SungKyunKwan Univ. VADA Lab. 12 Advanced routing for deep submicron technologies • • • • • • • • In the planning, what will make or break the design depends on whether the routing satisfies crosstalk and delay requirements, fits within available resources, and meets a host of other constraints. Routing is no longer a final batch-run step--it must be iteratively estimated and resynthesized. The route-planning operation functions as the "constructive estimator" of all relevant interconnect characteristics needed to make correct design-planning choices. The deep submicron design planner will use route-planning results in myriad ways to: Modify the floorplan (floorplan compaction and pin assignment derived from the top-level route planning); Determine new synthesis constraints (budgets for intra-block delay, block input/output boundary conditions); Modify the netlist (driver sizing, repeater insertion, buffer clustering); Determine placement directives for block layout (over-block routes will locally affect utilization factors within blocks); Determine performance-driven routing directives for block layout (wire tapering, spacing, shielding, etc.) Route planning entails hierarchical and area pin modeling, understanding power/area-delay tradeoffs in devices and interconnects, and the ability to perform and verify "intelligent" bus routing, timingand signal-integrity-driven routing, repeater insertion, tapering, shielding, interleaving, and so on. Clearly, an advanced routing tool with an out-of-the-box charter is required. SungKyunKwan Univ. VADA Lab. 13 Constraint-driven Routing • • • Routing approaches are often classified according to such axes as gridded vs. gridless, area-based vs. channel-based, full-chip vs. switchbox, etc. More detailed classifications distinguish between breadth-first (A* or maze) vs. depth-first (line probe) vs. pattern search, iterative (ripup-reroute) vs. combinatorial (multicommodity flow, linear programming with rounding) heuristics, right- vs. wrong-way-based routing resource models, and so on. Within this taxonomy, high-capacity ASIC routers typically employ gridded, area-based, N-layer, symbolic, switchbox, global+detailed, A* search, and iterative rip-up/re-route approaches. By contrast, routers for lower-capacity, auto-interactive, full-custom and chip-assembly applications (typically, evolved from high-end PCB tools) are distinguished by their use of gridless, shape-based, and full-chip approaches. Both types are effectively solving a wide range of today's leading-edge design problems. And each must evolve to deliver the constraint handling, functionality, and controllability needed for advanced routing in 2001. Advanced router technologies require a rich vocabulary and powerful mechanisms to capture, translate, enforce, and verify cost functions and the many constraints of deep submicron interconnects. To handle complex constraints and objectives, an advanced router will have to exploit wire widths, spacings, and shielding/interleaving and driver and repeater sizing. This suggests a shift to gridless, shape-based routing, since gridded, right-way-centric approaches are both unnatural and wasteful of layout resources. The overhead of shape-based routing is offset by the underlying design methodology. Block complexities will be limited by synthesis tools' ability to satisfy performance constraints, and interconnect complexity will remain tractable due to hierarchy. SungKyunKwan Univ. VADA Lab. 14 New Features in Routing • • • Other capabilities are required when detailed topology design affects interconnect parasitics in such a way as to render pre-routing estimates useless. Search mechanisms will change when iterative ripup/re-route no longer finds the topologies that satisfy given constraints. New utilities will "atomically" construct entire topologies to optimize delay, skew, and area/delay/power tradeoffs in arbitrarily costed layouts. The router will be empowered to perform logic resynthesis (gate splitting, buffer-inverter clustering) when gate-level netlists are synthesized with imperfect assumptions about the physical embedding. Detailed placement will also become part of interconnect design, as up to 50% or more of the design's cell instances are repeaters and inverters, and as resynthesis flows (based on pre-detailed routing) lose accuracy. For leading-edge designs, routing-directed, on-the-fly synthesis of cell layouts (i.e., an "infinite cell library") can be expected. The next generation will be distinguished from present-day methodology by its longer loops and added flexibility, as well as its "construct by correction" philosophy. Long loops stem from the need to "constructively estimate" deep into the design process (to the level of a gate-level netlist, placement, and detailed routing, even while performing early chip planning). Added flexibility stems from overlapping degrees of freedom that can be used to solve a given violation. For example, a crosstalk violation can be fixed by a combination of placement, net ordering, shielding, spacing, driver sizing, and repeater insertion. Together, these attributes suggest the advanced router must support a highly re-entrant and interactive use model. SungKyunKwan Univ. VADA Lab. 15 • • • • Toward convergence Fundamental methodology changes are in store for routing technology, including unification of previously disparate flow stages, and empowering the router to perform logic resynthesis and detailed placement. The greatest challenges may lie in integrating new routing technology within an effective, convergent, design-planning and implementation methodology. The first challenge is to make routing tools more predictable by upstream design steps. The CPU cost of "constructive estimation" (brute-force modeling by actually executing the router) can hamper the search of the design space, particularly when deeper lookahead is required. Hence, modeling of routing tools must receive greater attention. The second challenge is to establish appropriate "flow-internal links," so that the "design planner's route planner" can be an early consumer of constraints, simulation results, and other information from earlier flow stages. In tight loops, implementing such links with common data structures or common databases, instead of typical binary or ASCII interchange files, can afford substantial speed-ups. The third and greatest challenge is to improve the synthesis-analysis links, particularly within the parasitic extraction/performance analysis/interconnect loop. Determining cost-effective analysis methods, and melding traditionally distinct geometric databases from layout and verification, are critical to achieving the socalled "stage 3" routing capability that directly embeds physical performance analysis into constraint-driven interconnect synthesis. SungKyunKwan Univ. VADA Lab. 16 Future Trend • • • • Circuit designers, who once needed to know little about the physical details of their devices, must now have access to the physical design information, such as routability, wire load modeling and logic gate delay modeling. Without this information, designers cannot accurately predict timing delays and routability. This problem becomes more severe as semiconductor industry evolves to deep submicron technologies. In the past, most circuit designers only concern about the clock skew at the late phase of a design. If the clock skew is larger than the specified, they would try to decrease the speed of the fastest signal path by adding more delay or increase the speed of the slowest signal path by using a shorter path. These modifications are time consuming and can be disastrous. The modifications can introduce new problems and errors. In some unfortunate occasions, the whole designs are redone. A relatively new class of tools - floor planner, can assists designers to increase the speed of design and reduce the iteration cycles of passing circuit designs between circuit designers and layout engineers. Floor planner plans the distribution and locations of logic gates across a chip in early stage of a design. It tries to estimate the interconnect delay, logic gate delay, clock skew, power distribution and congestion at the beginning of a design. Knowing this information, circuit designers can determine how to modify their designs, such as chip size, pin locations, hierarchy of logic gates and clock tree structures earlier. Management also plays a subtle but significant role. Communications among circuit designers, fabrication engineer, tool developers and layout engineers are essential for a successful design. Each group needs to understand its role. For example, tool developers should address to other groups about the limitation and the tolerance of the simulation results; fabrication engineering should provide accurate and precise data of the logic gate characteristics. SungKyunKwan Univ. VADA Lab. 17 What Designers Think about Noise & SI Source: April 1997 Survey of 212 N.A. Design Teams Copyright 1997 Collett International, Inc. Signal waveform quality Clock skew Coupling noise Voltage drops Switching noise Signal delays Ground plane inductance Least Concern Greatest Concern . SungKyunKwan Univ. VADA Lab. 18 Collett . . International Inc. .