Transcript Impact of Gate-Length Biasing on Threshold-Voltage Selection

Impact of Gate-Length Biasing on
Threshold-Voltage Selection
Andrew B. Kahng ¶*
Swamy Muddu*
Puneet Sharma*
CSE¶ and ECE* Dept, Univ. of California San Diego
Outline
 Introduction
 Simultaneous Vth Assignment and Gate-biasing
 Threshold Voltage Customization
 Experimental Setup
 Results
 Conclusions
Introduction
 Leakage significant portion of total power
– High leakage  short battery life
1.4
1.3
1.2
1.1
1.0
0.9
30%
Normalized Frequency
 Leakage variability
20x
0
5
10
15
20
Normalized Leakage (Isb)
 Leakage reduction techniques
– Standby leakage: MTCMOS, source biasing, input-vector
control, transistor-stacks, etc.
– Runtime leakage: Vth assignment, gate-length biasing
Runtime Leakage Control
 Vth assignment
– High Vth reduces Idsat (speed) and subthreshold leakage
– Use low Vth for timing critical devices, high Vth for others
– Obtained by different doping concentrations for each Vth
 Increase in manufacturing costs
 Gate-length biasing [DAC04]
– Increase gate-length of certain devices
– Gate-length (Lgate) biasing reduces Idsat and subthreshold leakage
Gate-length (nm)
14
0
13
8
13
6
13
4
Leakage
Delay
13
2
13
0
1.2
1
0.8
0.6
0.4
0.2
0
Change of leakage and
delay (each normalized to Impact on
1) for an NMOS device in Leakage and
Delay
an industrial 130nm
technology
– Bias only non-critical devices  no deterioration in circuit speed
– Leakage variability considerably reduced
Outline
 Motivation
 Simultaneous Vth Assignment and Gate-biasing
 Threshold Voltage Customization
 Experimental Setup
 Results
 Conclusions
Simultaneous Vth Assignment & Gate-Biasing
 Advantages of Vth assignment
– More favorable leakage-delay tradeoff
– No increase in gate capacitance unlike biasing
 Lgate biasing cannot be used as a replacement
 Advantages of Lgate biasing
– No additional process cost
– Leakage variability reduction
– Finer control over leakage-delay
tradeoff
 Vth assignment and Lgate biasing can be used simultaneously
This work: How does Lgate biasing affect selection of Vth’s?
Vth Selection
 Foundries select Vth’s that yield large leakage reductions in
all designs
 For large leakage reduction:
1. Lot of cells must be assigned high Vth
2. Large per-cell leakage reduction on assigning high Vth
 Low Vth determines circuit performance
 High Vth determines power reduction
– larger per-cell reduction  increase high Vth
– larger #cells get high Vth assigned  decrease high Vth
  optimum Vth’s should be determined by leakage-delay
tradeoff and design’s slack profile
Contributions
 Evaluate effectiveness of foundry-selected Vth’s
– What is the best set of Vth’s?
– Several other Vth’s used alternatively and leakage reductions
estimated
 Estimate additional leakage reductions afforded due to Lgate
biasing
– Lgate biasing provides cost-effective leakage reduction
 Study impact of Lgate biasing on best Vth’s
– How does the set of best Vth’s changes when Lgate biasing also
available?
Outline
 Motivation
 Simultaneous Vth Assignment and Gate-biasing
 Threshold Voltage Customization
 Experimental Setup
 Results
 Conclusions
Threshold Voltage Customization
 To study impact of changing foundry-set Vth, artificially generate new Vth
– Modify VTH0 parameter in SVT SPICE model
 To test fidelity of new artificial Vth
– modify VTH0 of (foundry-set) SVT gradually
– compare Ioff and Ion characteristics with those of HVT / LVT
 Number of Vth’s limited by characterization runtime
Name
Vth (volts)
HHVT
0.437
HVT
0.402
HSVT
0.362
SVT
0.327
SLVT
0.292
LVT
0.257
LLVT
0.222
Outline
 Motivation
 Simultaneous Vth Assignment and Gate-biasing
 Threshold Voltage Customization
 Experimental Setup
 Results
 Conclusions
Experimental Setup
 VTH0 in 100nm device models modified to generate SPICE
for four new Vth’s
 Library characterization done with Cadence SignalStorm
v04.10 and Synopsys HSPICE
– Sequential cells not touched (13 frequently occurring cells used)
 Three testcases (AES, DES3, OpenRisc1200) synthesized
with Synopsys DC v2004.12
– Synthesis done iteratively with decreasing target clock cycle time to
achieve tight slack distribution
Testcase
# cells
LLVT
LVT
SLVT
Delay (ns)
Leakage (mW)
Delay (ns)
Leakage(mW)
Delay (ns)
Leakage (mW)
AES
22000
1.134
9.46
1.214
4.61
1.294
2.24
OR1200
37000
2.860
24.01
2.960
13.08
3.110
7.69
DES3
86000
1.081
36.31
1.106
18.08
1.160
9.08
 Leakage reduction obtained with a commercial optimizer
tuned for Vth assignment and Lgate biasing
Outline
 Motivation
 Simultaneous Vth Assignment and Gate-biasing
 Threshold Voltage Customization
 Experimental Setup
 Results
 Conclusions
Triple-Vth vs. (Dual-Vth + Biasing)
 Comparison of leakage reductions with triple-Vth and dual-Vth
90
with biasing
Leakage reduction (%)
80
70
LVT+SVT
60
LVT+HVT
LVT+SVT+HVT
50
LVT+SVT+Biasing
40
LVT+HVT+Biasing
30
20
10
0
AES
OR1200
Testcase
DES3
 Triple-Vth can reduce leakage by ~8% more than is possible with dual-Vth
 Dual-Vth combined with biasing can achieve almost the same reduction
Modified Choice of Foundry Vth’s
 For foundry low-Vth, HSVT yields
Leakage power (mW)
3.5
lowest leakage power
3
AES
2.5
HHVT
2
HVT
1.5
HSVT
SVT
1
 Reducing foundry set low-Vth does
0.5
not result in leakage reduction
0
LLVT
LVT
 For some designs, lowering low-Vth
Low Vt
10
9
DES3
8
Leakage power
 Foundry-set high-Vth may not
yield best possible leakage
reduction
7
HHVT
HVT
HSVT
SVT
6
5
4
3
2
1
0
LLVT
LVT
Low Vt
for some cells may result in creating
slack on their fanout, which can
then be used for high-Vth
assignment (higher leakage
reduction)
Vth Selection with Gate-Length Biasing
 For each (testcase, low Vth), change available Lgate biases
and identify optimum high Vth
Lower Vth
LLVT
LVT
SLVT
Max. Bias
Higher Vth
HHVT
HVT
HSVT
SVT
No bias
47.94
51.37
56.78
61.58
4nm
54.07
57.24
62.09
64.88
6nm
54.97
57.90
62.84
65.50
8nm
55.35
58.21
63.10
65.79
10nm
55.87
58.49
63.50
66.06
No bias
61.27
64.03
66.83
65.89
4nm
64.89
66.68
68.23
68.35
6nm
65.66
67.31
68.85
69.19
8nm
65.97
67.70
69.12
69.72
10nm
66.21
67.90
69.46
70.15
No bias
64.42
65.33
63.23
49.08
4nm
67.10
67.93
66.43
54.10
6nm
67.74
68.72
67.25
56.10
8nm
68.02
69.10
67.87
57.55
10nm
68.21
69.41
68.34
58.63
% leakage reduction for different high Vth’s with different gate biasing for AES
Outline
 Motivation
 Simultaneous Vth Assignment and Gate-biasing
 Threshold Voltage Customization
 Experimental Setup
 Results
 Conclusions
Conclusions
 Simultaneous Lgate biasing and threshold-voltage assignment
effective for runtime leakage control
 Experiments on large benchmarks with Vth-Lgate optimizer
indicate comparable quality of results for triple-Vth and dualVth with Lgate biasing (  a “low-cost alternative” )
 Foundry Vth’s cannot always yield best possible leakage
reduction
– Analyze slack distribution, netlist structure, leakage-delay trade-off to
choose or customize Vth’s
 Availability of Lgate biasing has a small impact on choice of
best high-Vth
– For well constrained design, best high-Vth reduces in the presence of
Lgate biasing