Transcript Leakage Current Mechanisms and Reduction Techniques in

Leakage Current Mechanisms and
Reduction Techniques in DeepSubmicron CMOS Circuits
Charbel Akl
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Outline
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Technology Scaling
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Transistor Leakage Mechanisms
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Leakage Reduction Techniques
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Conclusion
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Technology Scaling
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As technolgy advances, the number of transistors on a single chip
double about every 18 month
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Technology scaling
To Achieve higher density, higher performance, lower power
Technology Scaling
capacitances increase, frequency increase, therefore power
Vdd scaled down, so less performance and driving capability
Threshold voltage Scaled Down
Subthreshold current increase exponentially
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Technology Scaling
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With technology scaling, the channel length
become shorter and the oxide thickness less,
therefore leakage current increase
Short channel effects that causes Vth
reduction increase with decreasing channel
length
In general, the OFF-currents increase by 10
times per technology scale
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Technology Scaling
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Ioff is influenced by:
 Threshold voltage
 Channel dimensions
 Channel/surface doping
 Drain/source junction
depth
 Gate oxide thickness
 VDD
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Technology Scaling
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Technology Scaling
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Leakage Mechanisms
Main Leakage Components
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Reverse bias junction leakage (I1)
Subthreshold leakage (I2)
Gate leakage (I3,I4)
Other Leakage Components
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GIDL (I5)
Punchthrough (I6)
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Pn Junction Reverse-Bias
Leakage ( I1 )
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Flows between the drain and the well since they are reverse
biased, both in the on and off state.
Has 2 main components:
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Minority carrier diffusion/drift near the edge of the deplition region
Electron-hole pair generation in the depletion region of the reversebiased junction
Is a function of junction area and doping concentration
Mainly due to high doping concentration ( which is the case for
advanced MOSFETs for better SCE) which causes tunneling of
carriers across the junction
Dominates long channel devices off current
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Subthreshold Leakage ( I2 )
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Dominates modern devices off-state leakage due to the low
threshold voltage used.
Flows between drain and source when the gate voltage is below
the threshold voltage.
Increases exponentially as Vth decrease
Increases as channel length decrease
Reducing Tox reduce this current, but it will increase the gate
leakage at a high rate to an unacceptable level
Generally increases 10X per technology scale
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Subthreshold Leakage ( I2 )
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Subthreshold slope (St) indicates
the rate of decrease of Ioff
when Vgs goes below Vth
Measured in mv/decade (70120)
Low value of St is desirable
As Tox decrease St decrease
Increasing the doping
concentration ( to reduce SCEs)
increase St
Temperature and substrate bias
also can modify St
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Subthreshold Leakage ( I2 )
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Affected by different parameters:
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DIBL effect
Body effect
Narrow width effect
Channel length and Vth Rolloff effect
Temperature effect
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DIBL effect
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For long channels, source and drain are separated far
enough, hence Vth is independent of channel length
and drain bias
For short channels, Vth decreases as the drain bias
increase, this is known as DIBL effect
DIBL is enhanced at higher drain voltages and
shorter channels
Higher surface and channel doping reduce the DIBL
effect on the subthreshold leakage current
DIBL does not change St, however increasing the
doping to reduce DIBL increase St
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Other effects
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Body effect: Reverse bias well-to-source widens the bulk
depletion region and increases Vth.
Narrow Width effect: the decrease in gate width increase the
threshold voltage and therefore decrease the subthrehold
current, however the inverse also applies in trench isolation
devices
Vth Rolloff: threshold voltage decrease as the channel length is
reduced
Temperature: Is an important factor since VLSI circuits usually
operates at high temperature due to power dissipation. As
temperature increase, Vth decrease and subthreshold slope
increase. Therefore subthreshold current increase
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Inv. Narrow Width and Vth Rolloff
and temperature effects
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Gate Leakage
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Mainly due to tunneling of electrons from gate to
substrate and from substrate to gate (I3), and to hot
carrier injections (I4).
The high electric field coupled with low oxide
thickness lead to tunneling
With high gate leakage, transistors don’t have an
infinite input impedance anymore
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Other Leakage sources
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GIDL (I5) and Punchthrough (I6) are of secondary effect
Both GIDL and Punchthrough are off-state leakage currents
GIDL is due to the high electric field effect in the drain juction of
an MOS transistor, its effect is reduced by very high doping
profile
Punchthrough: As the channel length decrease, the separation
between depletion region boundaries decrease. Also as Vds
increase the jucntions are pushed near each others.
A solution for Punchthrough is to use additional implants and
doping at bottom or edges of the source and drain junctions
boundaries
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Leakage Reduction Techniques
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Architecture level
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Circuit level
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Pipelining
Transistor stacking
Dual Threshold CMOS
MTCMOS
VTCMOS
DVTS
Process level
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Changing dimensions, doping, changing process
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Pipelining
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Pipelining allow the circuit to operate at a lower Vdd
while keeping the same performance or throughput
as a no pipelined circuit
Lower Vdd means lower drain bias and hence lower
DIBL effect and lower gate leakage and lower
punchthrought
Lowering Vdd affects all power components including
leakage
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Transistor Stacking
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Subthreshold current reduces when flowing
throught a stack of two or more off
transistors
The voltage at intermediate nodes is positive
due to small drain currents.
Gate to source voltage becomes negative,
hence the subthreshold current reduces
The body to source potential becomes
negative, and the drain to source voltage
decrease, leading to an increase in the
threshold voltage.
More transistors in series, less leakage
current
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Transistor Stacking
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The subthreshold current depends on the applied input vector
More transistors switched off (especially NMOS) during standby
mode, less subthreshold current
This input vector is found using many techniques:
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Enumarate all combinations of inputs (for small circuits)
Random search-based technique for the best combination where
leakage evaluation is done for each input, and the vector that gives
minimal leakage current is chosen ( maybe not best vector)
Employing an algorithm that searches for the best vector among all
possible vectors ( genetic algorithm,..)
This technique is effective is reducing leakage standby current
for single Vth circuits
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Transistor Stacking
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To force the inputs to switch
to a certain low leakage
state during standby,
multiplexers and static
latches are used
This adds more hardware
hence more power
consumption, so it is best
suitable for circuits with
large standby time
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Dual Threshold CMOS
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Two types of transistors are fabricated on the same chip, one
type with low Vth and other with high Vth.
This can be done by many ways:
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Changing channel doping profile
Using different oxide thickness
Using different channel length
Using multiple body bias
Use low Vth devices to gain performance, and high Vth devices
to cut off leakage paths
Usually, low Vth devices are used for the critical path of the
circuit. High Vth devices are used in the non critical path where
performance loss does not affect the circuit performance.
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MTCMOS
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Inserts an extra series connected sleep transistor with high Vth in the
pull-up or pull-down path, and turns it off during standby mode
Use low Vth in the logic block to enhance performance, however the
extra series transistor will increase the delay during normal operation
mode, Hence this technique can be used only for non critical paths.
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MTCMOS
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The NMOS insertion scheme is preferable, since the NMOS onresistance is smaller at the same width; therefore it can be sized
smaller tham the PMOS
Only reduce leakage in standby mode, and the extra transistors
increase the area and delay
SCCMOS: instead of using high Vth sleep transistors, use low
Vth transistors with an inserted gate bias generator which uses
higher VDD and lower VSS during standby to fully cut off the
leakage current
Circuits can work at lower supply voltages
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VTCMOS
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A self-substrate bias circuit is used to control the body bias
In the active mode a zero body bias is applied. In the standby mode a
reverse body bias (RBB) is applied to increase the threshold voltage cut
off the leakage current
Reduces SCEs effectively
Recent research proposed using
forward body bias (FBB) where
the circuit is designed using high
Vth transistors to reduce leakage
in standby, and forward body bias
is applied during active mode to
enhance performance
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Dynamic Vth Scaling (DVTS)
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DVTS uses body biasing to adaptively change Vth based on the
performance demand. (active leakage reduction technique)
Low Vth through ZBB is delivered when high performance is
required, and high Vth through RBB is delivered when
performance demand is low.
A DVTS hardware uses continuous body biasing control to
determine the optimal Vth for a given workload.
DVTS hardware are sophisticated hardware and they use
feedback loop to continuously find the optimal Vth
A simpler implementation continuously switch between High Vth
and low Vth based on the performance demand.
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Process Level Techniques
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Modifying Dimensions
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Modifying the bulk-CMOS process by changing the doping profile in the
channel region
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Channel length
Oxide thickness
Junction depth
Retrograde doping
Halo doping
These doping techniques allow decreasing the channel length and increase
the transistor drive current without causing an increase in the off leakage
current
Use other process instead of bulk-CMOS
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SOI
SIMOX
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Conclusion
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With the continuous scaling of CMOS devices, leakage current is
becoming a major contributor to the total power consumption
Subthreshold and gate leakage have become dominant sources of
leakage and are expected to increase with the technology scaling
Many solutions have been developped to overcome the leakage
problem, some of these at the architecture level or the circuit level or
process level
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