Transcript Cadence`s Solution for High-Speed Design

Cadence’s Solution for High-Speed Design
Cadence Design Systems, Inc.
Agenda
What is High-Speed Design?
Ideal High-Speed Design Process
Introduction to SPECCTRAQuest Power Integrity
confidential
SPECCTRAQuest Demonstration
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The Day of “High-Speed” Has Come
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“Pc-board designers, meanwhile, were retooling in 1999
for high-speed design. Signal integrity, once confined to
high-end boards, has become everybody’s problem…”
Richard Goering, commenting on why the PCB layout market grew 20%
while the IC layout market shrunk 30%, in EETimes 4/10/2000 page 70
Welcome Networking!
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Hammerhead
Networks
Agenda
NOW
What is High-Speed Design?
Ideal High-Speed Design Process
SPECCTRAQuest Demonstration
confidential
Introduction to SPECCTRAQuest Power Integrity
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What is “High-Speed” ?
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Huh?
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Question: Which is a “High-Speed” Problem?
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Answer: They BOTH Are !!
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Definition of High-Speed
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A net can be considered ‘High-Speed’
when you have to do something other
than simply connect it.
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High-Speed Design Involves 2 Things
 Nets that are understood, and must be constrained
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 Nets that must be analyzed to be understood,
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and then constrained
 Nets that are understood, and must be constrained
SDRAM DIMM Layout
 Nets that must be analyzed to be understood,
and then constrained
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MODELS
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Datasheets
Front-side Bus Simulation
Most Tools Force You to Choose
Analyze
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Hmm...
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Constrain
But for High-Speed You Need BOTH
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Let’s Go!
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Analyze &
Constrain
All in ONE
integrated &
interactive
environment !
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SPECCTRAQuest: Integrated Constraint & Analysis
Model
Development
& Verification
Analyze
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Constrain
Pre-Route
Sol’n-Space
Analysis
Topology
Entry &
Floorplanning
Constraint
Driven
Layout
Post Route
Analysis
Verification
SPECCTRAQuest helps you manage the process
of High-Speed PCB development through both
Simulation Analysis & Constraint-Driven Layout tasks
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A Complete Solution!
Expanding Existing Process
HIGH-SPEED
Electrical
Model
Creation
rules/
criticals/
placement
/ ACs
Derive
Constraints
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Re-use
Topology
Topology
Topology
Files
Files
Files
SCHEMATIC
LAYOUT
Schematic
Model
Creation
Physical
Model
Creation
Schematic
Creation
Outline/
Floorplan/
Room Def/
“IP”
Library
netlist
constraints
PCB
Routing
Post-Route
Analysis
no
OK?
yes
BackAnnotate
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To Final Verification
SI Clean
Route
Agenda
What is High-Speed Design?
NOW
Ideal High-Speed Design Process
SPECCTRAQuest Demonstration
confidential
Introduction to SPECCTRAQuest Power Integrity
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Ideal High-Speed Design Flow
Analyze
Model
Model
Pre-Route
Development
Sol’n-Space
Development
& Verification
Analysis
& Verification
Constraint
Driven
Layout
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Constrain
Topology
Entry &
Floorplanning
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Development Process Flow
Post Route
Analysis
Verification
Need Flexible Device Modeling Language (DML)
Cadence
EBD
DML
Models
Package,
Transmission Line,
Connector, Cable
Models
Quad
Models
IBIS
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Version 2.1
Version 3.2
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SPICE
Models
can’t do “M”
element today
 Today’s models come in many styles and formats
 Cadence DML can model all formats AND advanced behaviors
(for example, Merced / Itanium)
Ideal High-Speed Design Flow
Analyze
Pre-Route
Pre-Route
Sol’n-Space
Sol’n-Space
Analysis
Analysis
Topology
Entry &
Floorplanning
Constraint
Driven
Layout
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Constrain
Model
Development
& Verification
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Development Process Flow
Post Route
Analysis
Verification
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Pre-Route Solution Space Analysis
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 Exhaustive “pre-layout” analysis of
manufacturing and design variances
 Used to define topologies, routing
rules and termination strategies
 Crosstalk and data pattern
dependencies may be taken into
consideration
 Swept-parameter analysis is used
extensively to cover all combinations
of conditions
 Need flexibility to define any kind of
simulation and any kind of
measurement criteria
Derive and Save “Solution Space”
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Constrain
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Analyze
Output of pre-layout process is an electronic constraint file
that can be used to guide the layout process
Ideal High-Speed Design Flow
Analyze
Pre-Route
Sol’n-Space
Analysis
Topology
Topology
Constraint
Entry &&
Driven
Entry
Floorplanning
Layout
Floorplanning
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Constrain
Model
Development
& Verification
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Development Process Flow
Post Route
Analysis
Verification
High-Speed PCB Design Now Requires Both
Electronic Inputs to Floorplanning & Routing
Topology
Files
Final
Netlist
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T
EC
L
E
LO
AL
C
I
R
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PCB
Routing
PHYSICAL
GIC
AL
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Topology Entry and Floorplanning
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 Design rules derived from solution
space analysis guide the placement
process
 Constraint Manager spreadsheets
plays a key role in guiding /
evaluating component placement
 Margin columns show difference
between constraint and design value
– Fast feedback
– Color-coded status
Ideal High-Speed Design Flow
Analyze
Pre-Route
Sol’n-Space
Analysis
Constraint
Topology
Constraint
Entry &
Driven
Driven
Floorplanning
Layout
Layout
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Constrain
Model
Development
& Verification
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Development Process Flow
Post Route
Analysis
Verification
Constraint Management Today
GUI
Exploration
HyperLynx
ePlanner/QUAD
GUI
?
SPICE
Constraints
Constraints
GUI
Floorplanning
?
ePlanner
ICX
?
Constraints
Layout
VeriBest
Board Station
PADS
Constraints
Constraint Manager
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Capture
Design
Architect
ViewDraw
GUI
SPECCTRAQuest
Exploration
ConceptHDL
Capture
SPECCTRAQuest
Floorplanning
Allegro/APD
Layout
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PSD 14.0 Constraint Manager
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 Common, powerful environment for constraint entry / editing / management and
verification
 Single mechanism for managing constraints throughout the design process
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Constraint Manager – Key Features
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 Spreadsheet-based graphical
interface
– No cryptic formats or
cumbersome updating
 Provides unsurpassed Integration
across the entire design flow
– Consistent Front to Back solution
– No messy translations with static
constraint data
– Directly integrated with
schematic and PCB databases
– Analysis engines can update
spreadsheet data interactively
Constraint Manager – Hierarchy
 Allows constraints to be managed hierarchically
– Groups of rules are maintained as Electrical Constraint Sets
(ECSets)
– Provides single point for updating rules or assigning to nets
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– ECSets can be applied to groups of nets (buses) with individual
overrides
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Constraint Manager – Systems
RIMM
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Termination
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Chipset
 Support for system level constraints
– Constraints can span PCB
boundaries
Constraint Driven Layout
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Guides:
 Floorplanning
 Hand Layout
‹#›Auto-Route
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Constraint Driven Layout
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 Design rule violations during
interactive routing are identified in
real-time
 Autorouter follows design rules powerful integration with
SPECCTRA!
 Because solution space analysis has
defined a set of conditions under
which the nets are known to work,
chance of first-pass success is high.
– Nets can be ripped up and
rerouted, as long as they still
adhere to the design rules
Ideal High-Speed Design Flow
Analyze
Pre-Route
Sol’n-Space
Analysis
Topology
Entry &
Floorplanning
Post Route
Post Route
Analysis
Analysis
Verification
Verification
Constraint
Driven
Layout
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Constrain
Model
Development
& Verification
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Development Process Flow
Agenda
What is High-Speed Design?
Ideal High-Speed Design Process
NOW
Introduction to SPECCTRAQuest Power Integrity
confidential
SPECCTRAQuest Demonstration
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SPECCTRAQuest
Power Integrity Module
The Future of Power Delivery System Design
Cadence Design Systems, Inc.
SPECCTRAQuest Power Integrity
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 Innovative technology developed and proven by Sun
Microsystems, now commercialized by Cadence Design
Systems, Inc. to address Power Delivery issues in high-speed
PCB System Designs.
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 A design tool / methodology used to design and optimize the
frequency-dependent characteristics of Power Delivery Systems
in high-speed system designs
 An integrated solution to allow many quick iterations of
“change-simulate-analyze”
Power Delivery Requirements Trend
Year
1990
1993
1996
1999
2002
Voltage
(Volts)
5
3.3
2.5
1.8
1.2
Power
(Watts)
5
10
30
90
180
Current
(Amps)
1
3
12
50
150
Zta rge t Frequency
(m-Ohms) (MHz)
250
16
54
66
10
200
1.8
600
0.4
1200
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 Power dissipation and longer battery life fueling decreasing chip power
supply voltages
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– Maximum allowable supply ripple decreases accordingly
 SoC, SiP fueling trend towards devices with large number of devices
– The instantaneous switching current required is enormous
 The maximum acceptable power supply ripple voltage determines the
target impedance which must be maintained across the PCB
– Maximum supply impedance must be less than 0.002 Ohms
Power Delivery System Design Challenges
 Power supply droop
– Alters system timing and can cause Setup failures
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– Can cause sampling errors that results in a system crash
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 Unreliable power delivery system design can cause increased
common-mode EMI preventing product shipment due to
compliance problems
 Power delivery system impedance is frequency-dependent
– Must be controlled for all frequency range of all transient currents
Increases Development Costs and
Time to Market is LOST!
Power Delivery System Design How it is done today
 Standalone analysis tools
– Design data translation is left up to the user
– Changes to the design resulting from simulation is manual
 Use Time Domain simulation
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– Power delivery system impedance is frequency-dependent!
– With only time domain simulation, it is like searching for needle in
a haystack
 Over design - add more de-coupling capacitors than necessary
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– Expensive solution that may not work
The Cadence approach
 Allow users to determine the needs of the power delivery
system
– Target impedance
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– Decoupling capacitor requirements
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 Provide frequency domain analysis to find problem areas
 Provide an integrated PCB design editor to optimize capacitor
placement
Develop reliable power delivery system
while shortening design cycle time
SPECCTRAQuest Power Integrity Software Components
 Frequency-domain analysis engine
 Integrated PCB editor that includes
Decoupling capacitor placement
environment
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 Impedance requirements calculator
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 Decoupling requirements wizard
 High speed capacitor library / library
editor
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Isolating Decoupling Problem Areas
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Device Placement – Decoupling Capacitors
 Capacitors can be selected from
the decoupling “menu” and
placed into the design
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 The effective decoupling radius
is automatically displayed as the
capacitor is positioned
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 Designers continue to adjust
capacitor selection & placement
until performance of the PDS is
acceptable
Allows many
“change-simulate-analyze”
cycles in a short time
Release
 Available with PSD release version 14.1
– Scheduled for late Q2, 2001
 First release available on Sun Solaris (7 / 8) only
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– Other platforms to follow with next major release
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SPECCTRAQuest Power Integrity - Summary
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 Innovative technology developed
and proven by Sun Microsystems,
commercialized by Cadence
 Combined toolset and methodology
for the design and analysis of high
performance power delivery systems
 Offered as an option to
SPECCTRAQuest, integrated with
Allegro
 Part of Cadence’s complete family of
Signal Integrity / Power Delivery /
EMI solutions
Shortens Development Cycle
and Time to Market!
Agenda
What is High-Speed Design?
Ideal High-Speed Design Process
Introduction to SPECCTRAQuest Power Integrity
confidential
NOW
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SPECCTRAQuest Demonstration
SPECCTRAQuest Demonstration
(please ask questions as we proceed!)
Cadence Design Systems, Inc.
confidential
What You Will See
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 Intel PIII / BX Reference Design
– 100 MHz Front-Side Bus
 Analysis & Constraint Process
– Board Level
– Electrical Level
– Constraint Integration
– Advanced Processing
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Post-Route DRC Verification
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 DRC checks identify areas which do
not comply with design rules
– Net is marked visually
– Identifies which constraint was
violated
 DRC provides a “first pass” check
faster than simulation
 Design rules can also be applied
without ripping up etch, to pinpoint
problems in boards routed before
design rules were available
Post-Route Analysis Verification
 Post-layout simulation now becomes
a “verification” process
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 Chances of first-time success are
high if a thorough solution-space
analysis was performed
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 Nets can be extracted individually
and analyzed in-depth if problems
are found
 SQ has the only optimized spice
analysis engine that is integrated
with PCB layout and field solvers
SPECCTRAQuest: Integrated Constraint & Analysis
Analyze
Pre-Route
Sol’n-Space
Analysis
Topology
Entry &
Floorplanning
Constraint
Driven
Layout
confidential
Constrain
Model
Development
& Verification
‹#›
Development Process Flow
Post Route
Analysis
Verification