Transcript Unique features of the proposed ZCS scheme - UIC

A Compact Bi-Directional PowerConversion System Scheme with
Extended Soft-Switching Range
Sudip. K. Mazumder, Liang Jia
Laboratory of Energy and Switching-Electronics System
Department of Electrical and Computer Engineering
University of Illinois, Chicago
Funding Agencies:
National Science Foundation (NSF)
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IEEE Electric Ship Technologies Symposium (ESTS’09)
Baltimore, Maryland
April, 2009
Overview of the Presentation
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 Introduction and Background
 Principles of the Proposed ZCS Scheme
 Operation modes of the ZCS scheme
 Unique features of the proposed ZCS scheme
 General Methodology and Optimization Method for the
Proposed ZCS Scheme
 General requirements for the ZCS scheme with nonzero
pulsating Dc output and the optimal ZCS range
 Particular examples for ZCS control condition
 Implementation of the proposed ZCS scheme
 Simulated and Experimental Validations for the Proposed ZCS
Scheme
 Key Conclusions
Introduction and Background



The need for realizing power-dense power-conversion modules that
support bi-directional power flow is an important factor for Navy and
Defense from the standpoints of reduced-footprint-space, weight, labor
cost, and mobility.
The existing megawatt class converters usually operate at low
switching frequency limited to about 1.2 kHz due to the limited turn
on/off performances of the high-voltage power devices, resulting in
high efficiency but, also yield bulky and costly magnetic materials
and filters.
New problems related to the high-frequency conversion schemes
occur, such as, low efficiency, high stress and high EMI, because of
the high frequency hard switching. One proper solution for these
problems is the soft switching technique.
Topology Overview for High-frequencylink Converter
Bridge I: Three single-phase full-bridge dc-ac converter
Bridge II: Three-phase active rectifier
Output voltage of the rectifier can be expressed as:
Vrec  MAX VU ,VV ,VW   MIN VU ,VV ,VW 
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Bridge III: Pulsating Dc/three phase Ac converter
Principles of the Proposed ZCS Scheme
 Implement the pulse-width and pulse-placement modulation (PWM & PPM)
scheme to make the switching control more flexible
 Take advantage of the features of three-phase rectifier to create the zero current
condition for Bridge I and zero voltage condition for the Bridge II
 Generate the voltage overlaps between lead and lag phases (considering the
leakage inductance of the HFL transformers)
 Regulate the average value of the rectifier output voltage equal to the sixpulsed modulated reference defined as: (u(t), v(t) and w(t) are the three-phase
sinusoidal reference signals, M represents the modulation index)
u  t   sin t

v  t   sin t  2 / 3

 w  t   sin t  2 / 3
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w t   v t 

u  t   v  t 
u  t   w  t 
ref  t   
v  t   w  t 
v  t   u  t 

 w  t   u  t 
ref 6  t   M  ref  t 
P1:  / 6  t   / 6
P2:  / 6  t   / 2
P3:  / 2  t  5 / 6
P4: 5 / 6  t  7 / 6
P5: 7 / 6  t  3 / 2
P6: 3 / 2  t  11 / 6
Modes of Operation of the Proposed ZCS
Scheme I
Mode 1:
 the top switches U2T and W1T
turn on
 Vu provides -Vdc and Vw provides
+Vdc to the secondary side
 the bottom switches V1B and
V2B are on, so Vv is equal to zero
Mode 2:
 VV supplies negative voltage to
the secondary side rectifier, and
VU is also negative
 the negative current from the
load side flows through the diode
DUB
 the top switch V2T is ZCS turn
on.
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Modes of Operation of the Proposed ZCS
Scheme II
Mode 3:
 U2T turns off and the voltage VU
equals zero
 the diode DVB will handle the
negative current
 U2T suffers a hard switching off
 Vv is negative since last mode, so
DVB endures zero voltage, which
creates a ZVS condition for DVB on
Mode 4:
 V1T turns on
 phase W supplies positive voltage
and the rest provide zero voltage to
the secondary side
 V1T goes on flowing the negative
current, so the switch V1T achieves
ZVZCS turn on.
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Modes of Operation of the Proposed ZCS
Scheme III
Mode 5:
 U1T switches on, therefore, the
VU will be +Vdc.
 DWT occupies the positive
current and DVB the negative one.
 based on the same principle as
Mode 2, U1T is ZCS turn on
Mode 6:
 W2T turns on.
 U1T starts taking off the
positive current and V2T still
handles the negative portion
of the current
 W2T is a ZVZCS turn on.
 DUT has a ZVS on
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Modes of Operation of the Proposed ZCS
Scheme IV
Mode 7:
 W1T turns off, and W2T begins to
handle negative current
 anti-parallel diode of W1T may
take off the negative current
 W1T is made a ZCS turn off
 this mode is similar to Mode 1
and DWB obtains a ZVS on
Mode 8:
V2T is off, and DUT (positive)
and DWB (negative) take the current
on the secondary side
 the current flows through V1T is
zero, which corresponds to a ZCS
turn off for V2T.
 this mode is similar to Mode 2.
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Unique features of the proposed ZCS
scheme
refW
refU
refV
t
t
W 1T
W 2T
t
U 1T
t
U 2T
t
V 1T
t
V 2T
t
VW
t
VU
t
VV
t
Vrec
t
ZCS edge
t0
10
t1
t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12
Switching waveforms of the proposed ZCS scheme
 The voltage Vrec on the
secondary side has only two
voltage levels: 2∙N∙Vdc and N∙Vdc
but no zero level
Advantage:
Less requirement for the clamp circuit
owing to the reduced parasitic device
body capacitance on the secondary side
under the nonzero voltage.
 Using linear programming to
implement the optimal solution
for the soft switching range
General Requirements for the ZCS Scheme with Nonzero
Pulsating Dc Output and the Optimal ZCS Range I
VW
1
1
VU
2
VV
3

2
The figure above is shown to denote the
definitions for phase voltage PWM widths (αi),
phase shift between phase voltages (βi) and the
width of gap (γ) for N∙Vdc. So the conditions and
constraints can be listed as follows:
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1  1  0

 2   2  0
      2
1
2
 3
1  1   2  0

 2   3   2  0
      1
2
 1
0   i  1  i  1, 2,3 

0   i  1  i  1, 2,3 
      2ref 6
1
2
 3
General Requirements for the ZCS Scheme with Nonzero
Pulsating Dc Output and the Optimal ZCS Range II
1  1  0

 2   2  0
      2
1
2
 3
1  1   2  0

 2   3   2  0
      1
2
 1
0   i  1  i  1, 2,3 

0   i  1  i  1, 2,3 
      2ref 6
1
2
 3
It can be expressed in the linear programming format:
 1 0 0 1 0 
 0 1 0 0 1 
where,
 Ax  b


0 0 1 1 1
lb  x  ub
A




1
0
0

1

1


 Aeq  x  beq
 0 1 1 0 1



min  f xT
0
0
0

1

1


 x


b   0 0 2 0 0 1
T
For the optimal ZCS range, we can define our
desired objective function as
min   f xT   min(1   2  1   2 )
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x
Implementation of the Proposed ZCS Scheme
1100
1000
Optimal value
1
2
3
1
2
900
800
700
600
500
60
70
80
90
100
110
120
DSP looks up data for optimization from an
inside embedded table, then packs,
compacts and transmits it to the FPGA with
2 WORDS.
Phase (deg)
2000

1950
1900
1850
To balance the power for each phase, we
can rotate the order of the gate signals
every 1/6 line period
1800
1750
1700
1650
60
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Solve the linear programming problem and
get the control coefficients for the ZCS
scheme (Plotted and rated at FPGA clock
signal frequency )
70
80
90
100
110
120
Particular Examples for ZCS Control Condition
I
VW
1
1
VU
2
VV
3
2

Case 1: Various-width-constant-phase-shift
The constraints for this case are:
2
3
4
 3  2ref 6 
3
1   2  3 
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1  1  0

 2   2  0
      2
1
2
 3
1  1   2  0

 2   3   2  0
      1
2
 1
0   i  1  i  1, 2,3 

0   i  1  i  1, 2,3 
      2ref 6
1
2
 3
And we can also fix
1   2  5 / 6
and the simulation waveforms will be shown later.
In this particular case, the modulation index M
should be
2
 M 1 .
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Particular Examples for ZCS Control Condition
II
VW
1
2
1
2
VU
VV
3

Case 2: Various-phase-shift-constant-width
The constraint for this case is:
1   2   3 
Also we can also set
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1  1  0

 2   2  0
      2
1
2
 3
1  1   2  0

 2   3   2  0
      1
2
 1
0   i  1  i  1, 2,3 

0   i  1  i  1, 2,3 
      2ref 6
1
2
 3
1   2  ref 6 
i
2
2
3
 i  1, 2, 3
to facilitate the implementation on the
hardware platform.
In this particular situation, the modulation
index M should be
1
 M 1
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1 kVA RHFL Converter Prototype
Main Components Used in the Prototype
 A 1 kVA RHFL-converter is designed to
validate the proposed soft-switching scheme.
 The designed input voltage is 36 V dc and
rated output voltage is 208 V ac (line to line).
 Switching frequency at Bridge I is 21.6
kHz and at the Bridge III is 43.2 kHz.
 Transformer turns ratio is around 1: 8.4.
Figure of the 1 kVA RHFL converter prototype
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Simulated and Experimental Validations
of the Proposed ZCS Scheme I
Switching
sequences
Diode current
and voltage in
Bridge II
Simulation result for Various-width-constant-phase-shift case
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Simulated and Experimental Validations
of the Proposed ZCS Scheme II
Experimental result for Various-width-constant-phase-shift case
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Simulated and Experimental Validations
of the Proposed ZCS Scheme III
Experimental results for the optimal soft switching range
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Measured Efficiency Comparison Result
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Key Conclusions
 The proposed ZCS scheme achieves 75 % ZCS for all the
switching actions on the Bridge I as well as ZVS on for the
secondary-side three-phase rectifier.
With a special objective function, a practical optimum solution
is given and two practical modulation conditions are also
presented.
Through the simulations and hardware experiments, all the
proposed ZCS situations are validated.
The overall efficiency of the prototype is measured to be
promoted compared with hard-switched Bridge I and II.
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Thank You!
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