Transcript Slide 1
EEG Machine
By
The All-American
Boys Featuring SloMo
Motaz Alturayef
Shawn Arni
Adam Bierman
Jon Ohman
High Level Block Diagram
WAVEFORM
MONITOR
PC/FOURIER
ELECTRODE
INPUTS
RAM
CPU
FLASH
USER INPUTS
AUDIO/VIDEO
OUTPUTS
Processor Schematic
FPGA Daughter Board
Power
JTAG
A2D
FPGA Pins
Bank 3
Bank 1
Bank 4
Bank 2
RS232
Push Buttons, Switches & LEDs
Sample Code using Nios II
• IP Core
– Ex. SPI
Void A2D_T (unsigned char ch){
while (true)
{
if(IOWR_ALTERA_AVALON_SPI_STATUS(base, data) &0x040)
{
IOWR_ALTERA_AVALON_SPI_TXDATA(base, data)
}
}}
Testing
• Memory Storage
– Inputs stored then flash LEDs
– FFT analysis to Nios II console
• RS232
– TX & RX LEDs, PC use
• User Output
– Flash On-board LED with Goggles
4
5
Contact
3
6
Con22
2
7
8
OPA27GU
1
2.5k
22
Input
D
N
G
Res3
22
Input
R1
4
1
0
0
1
50.5
Rsum2
3
Res3
6
2
RGain
Rsum2
2
7
8
INA105KU
5
2
Pre-Amp
Differential
2.5k
4
Res3
21
Input
R1
5
Contact
D
N
G
D
N
G
D
N
G
D
N
G
3
6
Con21
2
F
p
0
0
1
F
p
0
0
1
F
p
0
0
1
F
p
0
0
1
7
8
Semi
Cap
Semi
Cap
Semi
Cap
Semi
Cap
OPA27GU
1
Ground
C24
Diff
C23
Input
C22
Input
C21
21
Input
D
N
G
.4uF
Cap
Cf2
.2uF
4
G
Cap
Clp2
Res1
5
2
Rlp1
1
6
7
8
1
1
Cap
1
1
2
Output
OPA27GU
D
N
D
N
G
D
N
K
G
LowPass
F
p
0
Header
2
0
3
Rlp2
F
Res1
p
Cap
6
2
6
5
0
D
N
6
2
6
Res1
Cf1
1
K
D
N
G
Rgs
D
Cap
1
N
4
G
0
1
Clp1
G
5
Summer
Res1
12
Input
R1
F
OPA27GU
0
0
0
0
1
D
N
G
Res3
p
8
2.5k
12
Input
0
6
OPA27GU
F
5
1
8
p
7
7
1
0
Cs2
2
6
2
0
Cap
3
5
3
Con12
0
1
4
4
Contact
0
0
1
A
R
Res1
50.5
Rsum1
Cs1
3
B
R
Res3
Rsum1
6
1
RGain
2
7
8
INA105KU
D
N
G
5
1
Pre-Amp
Differential
2.5k
4
D
N
G
D
N
G
D
N
G
D
N
G
Res3
11
Input
R1
5
F
p
0
0
1
F
p
0
0
1
F
p
0
0
1
F
p
0
0
1
Contact
3
Semi
Cap
Semi
Cap
Semi
Cap
Semi
Cap
6
Con11
Ground
C14
Diff
C13
Input
C12
Input
C11
2
7
8
OPA27GU
1
11
Input
D
N
G
D
N
G
D
N
G
4
5
K
1
3
1
Res1
VccNeg
6
2
2
R1Vinv
7
8
VccPos
OPA27GU
1
Vinv
VccPos
K
1
Res1
R2Vinv
Electrode Input Schematic
Part Selection
• Op-Amp Choice:
– Burr-Brown OPA27
• Ultra low-noise amplifiers
• Differential Amp Choice:
– Burr-Brown INA105
• Ultra low-noise amplifiers
• Resistor Choice
– Using 1% tolerance, should be well matched enough
• Have .1% tolerance options picked out if necessary
Filter Selection
• Using Sallen-Key low-pass filter
– Corner at 100Hz
– 40dB/dec decrease
– Simple, easily expanded if necessary
– Should filter out high frequency noise
components to neural signal
• Filter not designed to filter out all
environmental noise
Power
• Input circuit powered separately from rest of
device
– Safety:
• Don’t want any risk with a person attached to one end
– Noise:
• High frequency components of processor could infect
power lines
– Introduce artifacts into signal
Power cont’d
• Input board powered by 9V battery
K
8
D
N
G
D
N
G
D
N
G
4
5
K
1
3
1
Res1
VccNeg
6
2
2
R1Vinv
7
VccPos
OPA27GU
1
Vinv
VccPos
1
Res1
R2Vinv
– Voltage inverted to provide negative voltage for
amplifier operation
Testing
• Testing will be done on PCB
– Voltage injections at specific input sites
– Measure response for each stage functionality
• Expect to see:
–
–
–
–
Amplification of 100x
Single summed output signal
Frequencies over 100Hz are not passed
Noise levels are minimized
Design Change to Contact
• No headband
– Movement and friction will introduce too many
artifacts
• Conductive paste will be necessary
– Metal/Skin interface is not good enough to
conduct strong signals
• Epoxy cast contact with double-sided adhesive
to form “well” for paste
Risks to Design/Implementation
• Cannot get usable signal from head contacts
– Purchase commercial contacts
• Low-Pass Filter not sufficient at eliminating
excess signal information
– Cascade to increase effectiveness
– Use Different Design
• Too much noise on the signal line
– Increase contact surface area
• Increase signal strength
– Isolate board through effective shielding
Output Component Changes
• Previous output components:
– Audio CODEC
– Monitor to display visual stimulus
• Current output components:
– Separate ADC and DAC
• Input signal is not being output as auditory stimulus
– LED mounted glasses or goggles for visual stimulus
• Eliminates the need for VGA circuit
ADC Architectures
Analog to Digital Converter
16-Bit Resolution
Low Noise Performance
Low Power Consumption
Sigma-Delta Architecture
Serial SPI Communication
Constant Output
Digital to Analog Converter
16 Bit Resolution
Serial I2C Interface
4 Channel Output
Low Power Operation
Output Directly to
Headphones
Visual Stimulus
Example of Glasses
Testing
•
•
•
•
•
•
Mount ADC to through-hole adapter
Input sinusoidal signal
View output on multi-meter
Mount DAC to through-hole adapter
Input digital values from FPGA flash
View output on oscilloscope
LabView code for PSD
TestResults
• The test used a .wav file
• The left graph is the time domain
• The right graph is the power
spectrum.
Serial interface
Buck conveter
•Buck converter used to supply enough current to the board.
(LM2676-3.3)
•VCCIO will power VCCIO1, VCCIO2, VCCIO3 and VCCIO4.
•VCC33 will power the ADC and the DAC chips.
•MAX232 need 3.3v so will use VCC33
•Memory
Power for Daughter Board
Voltage Regulator and Clock
•Voltage regulator with 1.2v output (LM1117-1.2-0.8A)
•VCC12 is the input for VCCD_PLL1, VCCD_PLL2, VCCA_PLL1 and
VCCA_PLLA.
•The clock is 50MHz
Schedule
Questions?