Transcript Final Presentation

HS DSL
PowerBench
Programmable Power Supply
Dror Lazar
Moran Fishman
Supervisor: Boaz Mizrahi
Winter Semester 2009/10
Project Overview - Reminder
A versatile power supply unit with
multiple outputs for laboratory use
and testing of various electronic
devices.
Project Overview - Reminder
User interface
Power
supply
Control unit
Measurement
unit
User interface for standalone
operation
LEDs
LCD
Keys
Active load
D
U
T
Overview – Control Scheme
DAC
Output
setting
Input
voltage
sense
Controller
Block
PWM
DC-DC
Post
Converter
regulator
& Registers
feed-
Auxiliary
Voltage
Sense
forward
ADC
Temperature
ADC
Current
limit
ADC
Microprocessor
Current
Sense Output
FPGA
Cypress FX2
USB Controller
USB
Cable
Voltage
Sense
FPGA Design
LEGEND
DATA
CONTROL
CLOCKS &
RESETS
SENSE A/Ds CONROL
PIC INTERFACE
CHANNEL 4
CHANNEL 3
CHANNEL 2
CHANNEL 4
CHANNEL 3
CHANNEL 2
CHANNEL 1
SPI 8-BIT
TRANSFER
SPI BUS
SPI
INTERFACE
DATA
SPI
DATA LINK
CHANNEL 1
GLUE
LOGIC
ADDRESS
DUTY
CYCLE
CONTROL & STATUS
FIFO BANK
PWM
CONTROLLER
PWM
GENERATOR
PWM
REFERENCE INPUT
REGISTER
BANK
DAC
INTERFACE
DAC CONTROL
SPI
DAC WORD
BUCK/CUK A/D CONTROL
BUCK/CUK
A/D
INTERFACE
CONTROL
SPI
BUCK/CUK A/D VOLTAGE
CYPRESS INTERFACE
CONTROL
Clocks, Buffers & Resets
LOGIC
24 MHz
CLOCKS & SYNC RESETS
DCMs
CLOCKS
ODDRs
SENSE A/Ds
DDR DATA
VOLTAGE SENSE DATA
16-BIT DATA
16-BIT DATA
IDDRs
BUFFERING FIFO
CURRENT SENSE DATA
FPGA input
Clock & reset
Control Scheme
FPGA Control Infrastructure

External Loop:
Determines VREF input for inner loop :
LDO POWER (Pref) = (Vref – Vout) * Iout
=> VREF = Pref/Iout + Vout
implemented using fixed LUT for Pref = 1W
Pref
Vout
Iout
LUT
Vref
FPGA Control Infrastructure

Internal Loop:
Regulates DC-DC converter
Implemented using Generic IIR FILTER :
1. Filter order and vectors width determined in FPGA
parameter.
2. Filter coefficients determined by software

Enables control design in PC environment (MATLAB)
and coefficient streaming to FPGA  Control algorithm
development without FPGA knowledge

Enables Same FPGA infrastructure for both DC-DCs :
Buck & Cuk Converter
Generic IIR Filter

Implementing in FPGA:
1. Filter sample frequency is different from FPGA system
frequency (much lower)
2. Sums of many vectors in one clock
2. Consecutive sums & multiples


If IIR filter module is operating in sampling frequency:
1. Low frequency is difficult to create
-> unwanted
2. Adds another time domain to the FPGA -> unwanted
Solution : 1. Avoiding direct implementation
2. Adding extra registers between calculative
operations
Generic IIR Filter
X[n]
a0
Y[n]
+
+
z
a1
+
+
1
Twelve
-
b1
z 1
a2
+
+
Allows
b2
z 1
a3
+
-
18x18 bit
multipliers in FPGA
b3
filter
an order 2 IIR
System Modeling
Vref
+
-
e
IIR
FILTER
K A/ D
PWM
K PWM
A/D
e  sTd
G(s)
Vout
System Modeling

Modeling the plant G(s) for buck & cuk
converters in continues time

Translating the continues time model to
discrete time model

Determining required control characteristics:
Steady state error, Overshoot, settling time
 Determining desired closed loop poles
System Modeling

Designing the IIR filter in MATLAB

Simulating the system in Simulink

Simulating the system in SPICE ?

Streaming (via USB) different sets of
coefficients to FPGA from PC

measuring analog response with scope and
comparing results
PC – FPGA communication

PIC software :
SPI module (PIC – FPGA)
PMP module (PIC – FX2)
FPGA soft-reset module

FX2 software :
PC enumeration (done by Greg)
End-Points configuration
Slave-FIFO configuration

Configure FPGA registers using PC :
PC => FX2 => PIC => FPGA => PIC => FX2 => PC
FPGA Firmware Updater
PC
Firmware Updater:
FPGA Firmware Updater
PC
 FX2  PIC  FPGA
•
Sending a vendor request to the FX2, setting an interrupt to
the PIC
•
Sending the data from the PC to the Cypress Bulk Endpoint
FPGA Firmware Updater
PC
 FX2  PIC  FPGA
•
Real Time Operating System is running on the PIC.
FX2 interrupt  PIC Task activation
•
Data transfer from the FX2 bulk endpoint to the PIC
FPGA Firmware Updater
PC
 FX2  PIC  FPGA
•
Data transfer from the PIC to the FPGA’s SPI Flash.
•
Flash  FPGA Firmware download
Questions
?