Transcript Mid Semester Presentation - High Speed Digital Systems Laboratory

HS DSL
PowerBench
Programmable Power Supply
Dror Lazar
Moran Fishman
Supervisor: Boaz Mizrahi
Winter Semester 2009/10
Presentation Contents

Project overview - Reminder

Current Status (What have been done)

What’s left
Project Overview - Reminder
A versatile power supply unit with
multiple outputs for laboratory use
and testing of various electronic
devices.
Project Overview - Reminder
User interface
Power
supply
Control unit
Measurement
unit
User interface for standalone
operation
LEDs
LCD
Keys
Active load
D
U
T
Overview – Control Scheme
DAC
Output
setting
Input
voltage
sense
Controller
Block
PWM
DC-DC
Post
Converter
regulator
& Registers
feedforward
ADC
Temperature
Auxiliary
Voltage
Sense
ADC
Current
limit
ADC
Microprocessor
Current
Sense Output
FPGA
Voltage
Sense
Current Status

FPGA design

Analog board bring-up

PC – FPGA communication
FPGA Design
LEGEND
DATA
CONTROL
CLOCKS &
RESETS
SENSE A/Ds CONROL
PIC INTERFACE
CHANNEL 4
CHANNEL 3
CHANNEL 2
CHANNEL 4
CHANNEL 3
CHANNEL 2
CHANNEL 1
SPI 8-BIT
TRANSFER
SPI BUS
SPI
INTERFACE
DATA
SPI
DATA LINK
CHANNEL 1
GLUE
LOGIC
ADDRESS
DUTY
CYCLE
CONTROL & STATUS
FIFO BANK
PWM
CONTROLLER
PWM
GENERATOR
PWM
REFERENCE INPUT
REGISTER
BANK
DAC
INTERFACE
DAC CONTROL
SPI
DAC WORD
BUCK/CUK A/D CONTROL
BUCK/CUK
A/D
INTERFACE
CONTROL
SPI
BUCK/CUK A/D VOLTAGE
CYPRESS INTERFACE
CONTROL
Clocks, Buffers & Resets
LOGIC
24 MHz
CLOCKS & SYNC RESETS
DCMs
CLOCKS
ODDRs
SENSE A/Ds
DDR DATA
VOLTAGE SENSE DATA
16-BIT DATA
16-BIT DATA
IDDRs
BUFFERING FIFO
CURRENT SENSE DATA
FPGA input
Clock & reset
FPGA Design

Clocks & buffers :
DCMs - internal clocks generation
IDDRs - sampling 2-channel A/Ds
ODDRs – clocks output to peripherals
Reset synchronization

Analog board interfaces :
1x
2x
2x
3x
4-channel A/D (sampling buck/cuk outputs)
2-channel A/D (sampling sensed current & voltages)
DAC (to LDOs and active load circuits)
PWM (to buck converters)
FPGA Design

Cypress FX2 interface
FX2 signals logic
High bandwidth data FIFO buffer

PIC microcontroller interface
Register bank
Data DPRs (with FIFO interface to PIC)
SPI interface : physical & data link layers

FPGA design Documentation :
Registers, operation modes, PIC interface, FX2 interface
Analog board bring-up

Chip/Circuit Validation :
1x 4-channel A/D
2x DAC
3x Buck converter
PC – FPGA communication

PIC software :
SPI module (PIC – FPGA)
PMP module (PIC – FX2)
FPGA soft-reset module

FX2 software :
PC enumeration (done by Greg)
End-Points configuration
Slave-FIFO configuration

Configure FPGA registers using PC :
PC => FX2 => PIC => FPGA => PIC => FX2 => PC
What’s Left

FPGA Design :
Learn about SMPS digital control techniques
Implement & simulate buck regulator controller (x4)
Implement Cuk converter interface

FX2 software :
Slave-FIFO interface change by PIC command (using INT)

PIC software :
Configure FPGA and FX2 to ‘Sensing mode’ and back
Burn FPGA’s FLASH (using SPI) by PC command
What’s Left

PC software :
Learn C++
Implement FPGA bit-stream download to on-board FLASH

Analog board bring-up :
Cuk converter debug and validation
LDO circuit debug and validation
Active-load circuit debug and validation
Sense A/Ds validation
Buck regulator validation
Questions
?