Transcript 014-EPROM

EPROM
PROGRAMMING
EPROM/OTPROM Module MTT48 V2.1 14 - 1
Module Objective
Learn the difference between EPROM and OTPROM.
Learn how to program the EPROM.
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EPROM MODULE
Clock
Generation
Module
(CGM)
System
Integration
Module
(SIM)
LVI
IRQ
COP
BREAK
RESET
68HC08
CPU
Timer
Interface
Module
(TIM)
Direct
Memory
Access
Module
(DMA)
Internal Bus (IBUS)
Serial
Communications
Interface
(SCI)
Serial
Peripheral
Interface
(SPI)
Random
Access
Memory
(RAM)
Electronically
Programmable
Memory
(EPROM)
Monitor
ROM
EPROM
• Erasable, 36 Kbytes ProgrammableOTPROM
• One-Time, 36 Kbytes Programmable ROM
• MCU without the quartz window can’t be erased
EPROM/OTPROM Memory Locations:
• $6E00 -$FDFF
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EPROM/OTPROM Control Register
EPMCR READ:
EPMCPD
$FE07
WRITE:
0
RESET:
0
0
0
0
0
0
ELAT
0
0
0
0
EPGM
0
0
EPROM Control Register (EPMCR)
•
EPROM/OTPROM Charge Pump Disable (EPMCPD)
– Used for reading EPROM at low voltage
– Disable pump if MCU is operating at 2.7 V or higher
1 = Charge pump disabled
0 = Charge pump enabled
•
EPROM/OTPROM Latch Control (ELAT)
– Latches the address and data buses for programming
1 = Buses set for EPROM/OTPROM programming
0 = Buses set for normal operation
– Clearing ELAT also clears the program control bit(EPGM)
– Data cannot be read when ELAT is set
•
EPROM/OTPROM Program Control (EPGM)
– Applies IRQ1/VPP voltage to EPROM/OTPROM
– ELAT must already be set to write to EPGM
1 = EPROM/OTPROM programming power switched on
0 = EPROM/OTPROM programming power swithced off
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EPROM/OTPROM
Programming Sequence
Sequence for programming a byte of EPROM/OTPROM:
1) Apply the programming voltage to IRQ1/VPP pin
2) Set the ELAT bit
3) Write to any EPROM/OTPROM address
– Note: writing to an invalid address prevents the programming voltage from being
applied.
4) Set the EPGM bit
5) Wait for a time, tEPGM .
6) Clear the ELAT and EPGM bits
note - Clearing the ELAT bit automatically clears the EPGM
– Setting the ELAT and EPGM bit with one instruction will set ELAT but clear EPGM.
– EPGM must be set by a separate instruction in the programming sequemce.
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Security
READ:
0
LVISTOP LVIRST LVIPWR SSREC
SEC
STOP
COPD
MOR
WRITE:
RESET:
UNAFFECTED BY RESET
Mask Option Register (MOR)
• EPROM/OTPROM Security bit (SEC)
– Prevents reading of the EPROM/OTPROM
– Writing to the MOR register has no effect
1 = EPROM/OTPROM security enabled
0 = EPROM/OTPROM security disabled
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Low Power
STOP mode
• Charge pump returns to VDD
Exiting STOP mode
• Charge pump resumes/stabilizes during oscillator start up
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Summary
EPMCR READ:
EPMCPD
$FE07
WRITE:
0
RESET:
0
READ:
0
0
0
0
0
0
ELAT
0
0
0
LVISTOP LVIRST LVIPWR SSREC
0
SEC
EPGM
0
0
STOP
COPD
MOR
WRITE:
RESET:
UNAFFECTED BY RESET
EPROM/OTPROM Module MTT48 V2.1 14 - 9