Transcript Mass of VL may be an Issue Close but not necessarily

(Subset) of ‘obvious’ Strip relevant architectures
Simplest (change/to implement) Architecture
Assume parallel strips forward and barrel
Pixels with amplifier/discriminator – are individual trims needed
Logical OR at strip end – area?
1% dead in 2.5cm long strip – recovery time 25mm/pixel length x 25ns (?x3)
ABCn modified to accept digital signal – very similar design to existing barrel
Thinned sensors – post processed with metal to help with routing?
Either uncut 10 x 10 with reticule sized strips or
Assembled 10 x 10 on thin substrate – how large gaps?
Voltage – 20V ?
Reticules or
Operating temperature – 20C ?
separated
Power – 10W/(10x10) sensor ?
Some x0 gain,
possible cost gain – sensors – HV system –
Possible stability gain – warm operation
Stitching of ‘marginal’ value?
Issues pertinent to all architectures, not repeated
Most Advanced Architectures
Integrate ABCn into sensor
Above pixel/strips – or to side would be a good geometry – requires stitching?
Hybrid to connect ABCs between reticules or separated sensors, caps, power..
Significant x0 gain
‘ABC’
sensor
Triggerless Readout
Abandon ABC as too complex to integrate on schedule
Group strips into ~100s, pixel has short data driven pipe (like PiMMs)
sparsify and ship out to local VL – need one 450Mbit/s output per 100 strips
Bandwidth wise, ~3 VLs per 10 x 10 area
Can sparsification and part of VL function be added at edge of sensor?
Is this simpler/faster to implement than ABC integration?
How much area at edge of strips to do logic - acceptable dead area?
100 strip
450Mbit/s copper to VL
Sparsification/VL conversion
Local VL
Mass of VL may be an
Issue
Close but not necessarily
practical
10cm x 10cm ‘sensor’
2.5cm x 80mm synthesised strips
48 groups of ~ 100 strips
~ 5k strips x 40MHz = 200Gbit/s
X 1% = 2Ghit/s
X (ln(100)/ln2 + ln(16)/ln2) = 22Gbit/s
7 + 4
22G/48 = 458Mbit/s copper line
Vertical pair, 100mm track and gap w = 200 x 48 = 9.6mm
This is very close for a 10 module stave, and difficult for 13.
But not a mile away.
Embedded sparsification/short pipe
458Mbit/s copper line per 100 strips 100mm gap and track
2 x 10Gbit/s link per module [~50k links total cf CMS]
Intermediate Architectures
Stereo
And axial hybrids
Both coordinates from single sensor
Gang logical output from pixel in different directions
Simulated stereo
Use ABCn modified to take digital input
Same issues as simplest implementation
Significant x0 gain
Add logic in pixel to generate address – how many bits (1mm resolution?)
Modify ABCn to store ? 5 bits rather than one per hit.
Can this be done without making a strip dead for 5 crossings?
Is five times larger pipeline realistic in ABCn
Map outputs into a version of FEI4/5 chips?
Geometry?