Transcript PowerSuppliesCALO - Indico

Power Review:
Calorimeters
D. Gascon for the LHCb calo group
Universitat de Barcelona
Institut de Ciències del Cosmos ICC-UB
LHCb - Electronics Upgrade Meeting – 11th October 2012 – CERN
I. Introduction
• The upgrade concerns the front-end electronics only
 Want to keep unchanged the rest of the electronics
 Do not change the corresponding power supplies
• HV for the CW
• HCAL Calibration system with Cs source
• The constraints for the front-end electronics
 Purpose is to keep unchanged as many systems as possible
 The front-end boards have to be re-designed
• Used linear regulators → availability for the upgrade is doubtful
• DC-DC convertors being designed at CERN could be a replacement
– http://project-dcdc.web.cern.ch/project-DCDC
• I will discuss only the DC-DC convertor solution
 Discussions (G. Blanchot) indicate Magnetic field should be ok
 Radiation is not a problem either (for AMIS chip family)
 Noise → this is being tested: preliminary results OK!
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I. Introduction
• DCDC converters developped by CERN group
Power distribution with
DC-DC converters
Vin
Buck Converter
High side
Specifications:
Vin<=10V
Control
Circuit
Vout
Phase
Cout
Vout=1.2-3.3V
Iout<=3A
frequency=1-3 MHz
Constrains:
Low side
DC/DC ASIC
magnetic (2T-4T) fields
gnd
radiation (TID>100Mrd,
fluence > 2 1015 p/cm²
ions with LET<40MeV·cm²/mg)
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S. Michelis, Twepp 2012, Oxford
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II. Powering scheme
• To reduce the cost, we would like to use the present Maraton
(Wiener) power supplies to power the DC-DC convertors
• Wiener designed several types of modules for the Maraton PS
 Most of them have an output voltage larger or equal to 8V
 Our modules are limited to 7V !
• Tested a spare Maraton on the PH-ESE test bench (V. Bobillier)
– 7V max at max power
• DC-DC nominal Vin is 10 V, although usually tested 6 to 12 V
 Need to check carefully for final AMIS chip and required Vo & Iload !
 Assume that DCDC can deliver 3A in any of the combinations 4
III. Powering requirements: ECAL/HCAL FEB
• Analog Shapers
 ASIC design → Vo = 3.3 V Iload=1.6 A
 A Vref=1.65 V (160 mA) is also needed
– Low power: DCDC not needed
– Generated by ASIC or using ADC Vref + OpAmp
 COTS design → Vo= +/- 3V Iload= 3.2 A
• Negative DCDC converter recently available (With positive input voltage)
• We will test also single supply scheme (+ 6V)
• ADCs
 Analog Vo = 3.3 V Iload=1.8 A
 Digital Vo = 3.3 V Iload=0.16 A
• Digital part: PGAs
 Core → Vo = 1.5 V Iload=6 A
 IO → Vo = 2.5 Iload=2 A
 IO → Vo = 3.3 Iload< 1 A
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III. Powering requirements: ECAL/HCAL FEB
• Optical link (many assumptions on conssumption)
 4 x GBT → Vo = 1.5 V Iload<4 A
 4 x GBLD → Vo = 2.5 V Iload<1 A
 4 x GBT-TIA → Vo = 2.5 V and 1.5 V Iload<1 A (both)
• GBT-SCA
 CORE: → Vo = 1.2 V Iload< 0.1A)
 IO → Vo = 2.5 V Iload< 0.1A)
• SLVDS to LVDS translators?
 1.5 and 2.5 V
• +5? V or -5? V → to be confirmed (NIM translators, etc...) ?
 Studying if possible to power at +3.3 V / -3.3 V (or remove)
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III. Powering requirements: ECAL/HCAL FEB
• Preliminary table (ASIC shaper)
 Many uncertainties
 Assume DCDC can deliver up to 3 A
Voltage [V]
Iload [A]
Shared by
DC-DC
3.3 Analog Shaper
1.6
ASICs
1
3.3 Analog ADC
1.8
Only ADC
1
3.3 Digital
1.16
ADC, PGA IO
1
2.5 Digital
5.1
PGA IO, GBT-SCA IO
2
1.5 Digital
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GBT&Co, PGA Core
4
1.2 Digital
0.1
GBT-SCA Only one…
1
-3.3 V
0.1
NIM
1
• That means 10 positive and 1 negative DCDC modules
• DC-DC input current: about 10.1 A
 For a 7 V input and with DCDC efficiency > 0.65
• Crate with 16 FEBs + 1 CB: 7 V requires < 170 A (4 Maraton modules)

Assume CB requires only digital part (7.6 A)
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III. Powering requirements: ECAL/HCAL FEB
• Preliminary table (COTS shaper)
 Many uncertainties
 Assume DCDC can deliver up to 3 A
Voltage [V]
Iload [A]
Shared by
DC-DC
3 Shaper
3.2
COTS
2
3.3 Analog ADC
1.8
Only ADC
1
3.3 Digital
1.16
ADC, PGA IO
1
2.5 Digital
5.1
PGA IO, GBT-SCA IO
2
1.5 Digital
12
GBT&Co, PGA Core
4
1.2 Digital
0.1
GBT-SCA Only one…
1
-3 V
3.3
COTS, NIM
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• That means 11 positive and 2 negative DCDC modules per FEB
• DC-DC input current: about 13.22 A
 For a 7 V input and with DCDC efficiency > 0.65
• Crate with 16 FEBs + 1 CB: 7 V requires < 219 A (5 Maraton modules)

Assume CB requires only digital part (7.6 A)
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III. Powering requirements: other boards
• Control board (new board)
 Blocks shared with FEB: Optical link, PGAs, GBT-SCA, etc..
 We assume that same power configuration as for FEB works
• Validation board
 Same as currently used (PGAs are reprogrammed)
 Need to keep Maraton settings:
• Only using 3.3 V
• Must be compatible with settings for DCDCs in FEB (7V)
• LEDTSB board (LED control & interface to TFC)
 Same as currently used: same concern as validation
•
~1A at +5 V, ~2A at +3.3 V and ~0.1 A at -5 V.
 But probably this can be reallocated in PS/SPD crates
• If PS/SPD not in the upgrade which looks quite probable
• Re-cabling needed !
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IV. Maraton configuration
• Present PS configuration:




+5 (Analog) / 100 A (2 modules)
-5 (Analog) / 50 A (1 module)
+3.3 (Digital) / 100 A (2 modules)
+5 (Digital) / 50 A (1 module)
• If 4 modules are required for 7V (DCDCs) :




+5 (Analog) / 100 A (2 modules) to + 7 V
-5 (Analog) / 50 A (1 module) to + 7 V
+3.3 (Digital) / 100 A (2 modules) keep for Validation Board
+5 (Digital) / 50 A (1 module) to + 7 V
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IV. Maraton configuration
• If 5 modules are required for 7V (DCDCs):
 +5 (Analog) / 100 A (2 modules) to + 7 V
 -5 (Analog) / 50 A (1 module) to + 3.3 V for Validation Board
• Rework in validation would be required
 +3.3 (Digital) / 100 A (2 modules) to + 7 V
 +5 (Digital) / 50 A (1 module) to + 7 V
• Power our system only partially with DC-DC convertors ?
 Actually our ADC are directly powered by the Maraton (no regulator)
• Works well
 Keep the present Maraton: 6 modules
 But change the configuration in order to power
• Partly our electronics directly
• Partly the electronics through the DCDC convertors
• Anyhow many assumptions and uncertainties are made !!!
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VI. Requirements and assumptions
• Requirements:
 To be able to operate the DC-DC converters
at Vin ≤ 7V
 To be able to obtain Vo from 1.2 to 3.3 V
with this input voltage
 About 250 boards (FEB + CB):
• About 3000 positive DCDCs
• About 500 negative DCDCs
• Assumptions:
 Output current: up to 3 A
 Power efficiency > 0.65
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