Transcript Electronics Test Benches @ GRAPES -3

Electronics R&D Projects
@
GRAPES -3
in collaboration with VIIT Pune
Atul Jain
On Behalf of GRAPES-3 Collaboration
WAPP – 2011, Bose Institute, Darjeelig
18th December, 2011
FPGA based 8 Ch. Scalar (2010-2011)
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Input
Translator
FPGA
USB
Interface
PC
SALIENT FEATURES
Team
 USB Interface
 Prof . S. D. Kale (VIIT)
 Low Power
Consumption
 Rohit (VIIT)
 Programmable features
 Atul Jain (CRL)
 Jatin (VIIT)
 R. Sureshkumar ( CRL)
Implementation
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 Development boards for Atmel FPGA
 PCB for Input Level Translator and microcontroller
mounting.
 GUI for Windows
Real World Test
4
365
#503_1min
FPGA_1min_503
12th JULY 2011
SRH_1min_503
Ratio
360
104
102
100
Rate/sec (Avg of 1 min)
98
355
96
94
350
92
90
345
88
86
340
84
82
335
00:00:00
80
01:00:00
02:00:00
03:00:00
04:00:00
05:00:00
Time
06:00:00
07:00:00
08:00:00
09:00:00
10:00:00
12th JULY 2011
353
FPGA_60min_503
#503_1Hr
SRH_60min_503
104
102
Ratio X 100
352
100
351
98
Rate/Sec (Avg of 1Hr)
96
350
94
349
92
90
348
88
347
86
84
346
82
345
00:00:00
80
01:00:00
02:00:00
03:00:00
04:00:00
05:00:00
Time
06:00:00
07:00:00
08:00:00
09:00:00
Projects for 2011-2012

 Hardware
 32 Ch. SCALAR with USB interface



64 Ch. SCALAR with Trigger Logic
and TCP/IP interface
High Voltage and Current
Monitoring and Recording using
USB intreface
Voltage & Temperature monitoring
along with Voltage control for SiPM
Software

Web interface for ROOT Monitoring

Root Program Development

Data Base Management for all
activities at GRAPES -3

GRAPES-3 Web page hosting at
Ooty with active link to all
Monitoring and DBMS
1 . FPGA based 32 Ch. Scalar
Input
Translator
FPGA
USB
Interface
PC
SALIENT FEATURES
Team
 USB Interface
 Prof . S. D. Kale (VIIT)
 Low Power Consumption
 Bhaskar Taneja (VIIT)
 Programable features
 Abhisekh Gupta (VIIT)
 On Board Real Time Clock
 Suraj Kole (VIIT)
 GUI for Linux
 Atul Jain (CRL)
 K.Manjunath (CRL)
 R. Sureshkumar ( CRL)
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9
10
11
32 Ch Scalar PCB
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In House Soldering
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Status
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 Board under test at VIIT
 GUI development for Linux
 Early January ready for test bench demonstration
2 . FPGA based 64 Ch. Scalar and Trigger module
with TCP/IP Protocol
Input
Translator
FPGA
TCP/IP
Interface
PC
SALIENT FEATURES
Team
 TCP/IP Interface
 Prof . P. Khandekar (VIIT)
 Low Power Consumption
 Rahul Wagh (VIIT)
 Programmable Trigger
 Harshad Surdi (VIIT)
 Data Recording and
control can be remote
 Akshay Pedhiwal (VIIT)
 Atul Jain ( CRL)
 B. Rajesh( CRL)
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BLOCK DIAGRAM
OPTO – ISOLATOR
AND LEVEL
CONVERSION
Opto-Isolation and Level Conversion
• Conversion from TTL to
LVTTL
• Discriminator: TTL (5V)
• FPGA: LVTTL (3.3V)
• Opto-Isolation: To get a clean digital pulse
Memory Management
SPARTAN6 LX9 FPGA
Counter , Trigger Logic
SPARTAN6-LX9 FPGA
• For counting the input pulses of 64 channels
• Defining a block of memory to store the count and its management
FEATURES:
• 60 to 160MHz Reference Clock support
• TQG144 package with 102 user I/Os
• 9,152 logic cells and 11,440 Flip-Flops
LPC2478 Micro-controller
• On-chip Ethernet, USB , UART, CAN, SPI support
• ARM7TDMI-S processor, running at up to 72 MHz
• 512 kB on-chip flash program memory with ISP and IAP
• 98 kB on-chip SRAM
• LQFP208 package with 160 GPIO pins
LPC2478
ARM7 Core based Micro-controller
CAN
USB
RS232
RS485
SRAM
Ethernet Transceiver: DP83848
• Temp Range: -40 to 85 C
• Single Port 10/100 Mb/s
• MII support
• An embedded web-server can be implemented and stored in the flash
memory which will facilitate the user to access the information about
each board through any web-browser
Data-Logging
• GUI in LINUX
FLASH
MEMORY
ETHERNET
TRANSCEIVER
PC
GUI
Future Long term Applications
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 Scheme would be adopted for

Designing compact and portable test benches

Enhancing the monitoring of parameters

Large DAQ to be installed at GRAPES-3
( 4000 nos of Proportional Counters)
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THANKS