Transcript VIIT-GRAPES3 Collaboration

Dr. C. S. Garde
Vishwakarma Institute of Information Technology, Pune
VIIT, Pune
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Experimental Physics – Technology intensive
Devising new Experiments using cutting edge
Technology – a must for new Physics
However, limited time and manpower for
research in technology
VIIT has a large pool of engineering faculty
(~130) and students (500 in final year)
Win-Win situation
VIIT, Pune
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VIIT, Pune
Design of Si Photo Multiplier (SiPM)
Field Programmable Gate Array (FPGA)
based high speed counter
Power supply for SiPM
Photomultiplier tube DAQ
Web Interface for ROOT monitoring
Binary to ROOT conversion using ROOT
framework
Inventory
Management
System
for
GRAPES-3
Year
No. of
projects
No. of
students
No. of
faculty
(VIIT)
Departments
2010-2011
4
12
4
Electronics
2011-2012
7
22
7
Electronics and
Computer Engg
VIIT, Pune
VIIT, Pune
1)
2)
3)
4)
5)
6)
7)
VIIT, Pune
Design of Si Photo Multiplier (SiPM)
Field Programmable Gate Array (FPGA)
based high speed counter
Power supply for SiPM
Photomultiplier tube DAQ
Web Interface for ROOT monitoring
Binary to ROOT conversion using ROOT
framework
Inventory
Management
System
for
GRAPES-3
Design of Si Photo
Multiplier (SiPM)
VIIT, Pune
• Tool: Silvaco TCAD 2010
• Uses Maxwell’s and Poison’s equation.
• Started with simulation of P-N junction diode structure in
reverse bias mode.( APD is just P-N junction operated
above breakdown voltage)
• First Mesh was optimized and it is chosen as 0.01 microns
at Junction.
N+
P
• Simulations were done by varying n-type and ptype concentration,keeping other parameters
fixed.
• Effect on breakdown voltage was observed and
results are plotted.
• P-type concentration Varied from 1e15 to 1e17
• N-type concentration Varied from 1e18 to 1e20
• Each range was broken into 10 points , so total
100 simulations.
Net Doping(/cm3)
Brekdown Voltage(V)
Breakdown Voltage Vs n-type concentration
20
16
12
8
4
0
1.00E+18
Fig. 1
5.10E+19
1.01E+20
Fig.
2
n-type concentration(/cm3)
Breakdown voltage depends on concentration of lightly doped side,
here p-type side .Plotted graph (Fig. 1) shows the similar relationship as
given in theory.
(Semiconductor Device Fundamentals
- Robert Pirret)
Practical doping
• Till now structure simulated as a step junction (abrupt
junction) which is ideal case
• Practical methods of doping : Ion Implantation and
Diffusion
• Diffusion : a error-function doping profile.
• Ion Implantation : a Gaussian doping profile.
Net Doping Profile for Step ,Gaussian and error function
I-V curve for different doping profiles
Cathode current and capacitance
Capacitance :
Optical Simulation
• Spectral Response
• Transient Response
With appropriate biasing(reverse) Optical pulse of very short
diode is bombarded with light of duration is incident on surface of
various
wavelength
covering diode.
visible spectrum.
Current
through
diode
is Diode’s response (rise time, fall
monitored and plotted as function time) is studied .
of wavelength.
Spectral Response at different biasing voltages
In any optical simulation for simple n+ p structure, reflections from top surface is not
considered
Depth of n-type region was varied from
0.1 to 2.5 um and spectral response was
taken at every depth, keeping light
intensity constant.
Results
were plotted for 580nm
wavelength.
Peak was observed at 0.3 um.
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Cathode Current(A)
Cathode current vs n+ depth
5.00E-007
4.50E-007
4.00E-007
3.50E-007
3.00E-007
2.50E-007
2.00E-007
1.50E-007
1.00E-007
5.00E-008
0.00E+ 000
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
n+ Depth(um)
Intensity Variation at various n+ depths
Simulations were also done by
changing input light intensity at various
n+ depths
keeping wavelength
constant at 580nm.
Cathode current (A)
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Exactly same results were obtained
as of previous simulation,which
confirms the results.
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Plotted graphs show considerable
increase in current at depth of 0.3um.
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Penetration depth of silicon at 580nm
is 2um, which can be confirmed by
decline in currents at higher depths.
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Transient simulation( P-Spice)
We could not obtain Transient
response in P-Spice environment,here
Cathode current pulse( Green) is
much smaller than Available photo
current pulse, which is inappropriate.
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Problem might be in migrating from
ATLAS environment to P-Spice
environment.
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So, we decided to simulate transient
response in ATLAS environment
without external quenching resistance.
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Cathode Current(A)
At 75.25V – just at breakdown (Atlas)
Rise Time=1.2ns
Input Optical Pulse
At 75.27V – above the breakdown
77.5
77
y = 0.051x + 59.87
Breakdown Voltage (V)
76.5
76
75.5
75
74.5
74
n concentration = 1e18
p concentration= 6.3e15
73.5
73
250
260
270
280
290
300
Temprature ( °C)
310
320
330
340
Variation of temperature
coefficient with n type conc.
Temperature coefficient (V/°C)
0.052
0.0518
0.0516
0.0514
0.0512
0.051
0.0508
0.00E+00
1.00E+20
2.00E+20
n type concentration (\cc)
As n concentration is varied temperature coefficient does not vary much
(the graph shown above is zoomed in)
0.25
Temperature coefficient
0.2
0.15
0.1
0.05
0
0.00E+00
5.00E+16
p type concentration
1.00E+17
Parameters
P conc.
(/cc)
Breakdown
voltage (V)
Capacitance
(F/mm)
Temperatur Peak value
e coefficient of E field
(V/oC)
(V/
4e15
101
0.15e-14
0.07
3.5e5
6.3e15
75
0.25e-14
0.05
3.8e5
1.6e16
41
0.4e-14
0.02
4.5e5
2.5e16
32
0.5e-14
0.02
4.9e5
Towards new structure...
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Till now we have simulated only simple p-n
junction(device simulation) in order to understand effect
of every parameter.
So we moved on to the more practical structure, which is
made up of 4-5 layers.
Gain=32 at
Breakdown
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Process simulation started
After fabrication, simulations can be fine tuned for
development of full fledged SiPM
Web Interface for
ROOT monitoring
VIIT, Pune
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Object-oriented program and library.
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Developed by CERN.
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Designed for particle physics data analysis.
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In other applications such as astronomy and data
mining.
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Parts of the abstract platform are:
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Graphical user interface and a GUI builder
Container classes
Reflection
C++ script and command line interpreter
(CINT)
Object serialization and persistence
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Recorded data sent to collaborators by
post/courier in DVDs
Every collaborator needs to know and
memorize various commands of root
Access to data is not instant, as DVDs sent
every week.
Our Goal
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To develop a system for web monitoring of
ROOT data and remote execution of ROOT
commands.
System will generate graphs, images and
necessary information required by
collaborators of TIFR for analysis of data
depending upon input provided by user
through GUI.
Weather
PARAMETER
Temp (In)
BIN SIZE (minutes)
TIME RANGE
Start
Date
Time
Default
End
Temp (Out)
Pressure
Humidity
Rain
Weed Speed
PLOT
Date
Time
Our Approach
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As a result of VIIT-GRAPES-3 collaboration,
VIIT students are motivated to take up
research careers
VIIT faculty also benefiting from hands-on
experience
Developing valuable Human Resource
Strong VIIT-GRAPES-3 collaboration could
help GRAPES-3 to upgrade the existing
experiments and possibly take up new
challenging experiments
VIIT, Pune
VIIT, Pune
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Pulse signals from the Scintillator Detectors are digitized in
the discriminator section and fixed width pulse is taken as an
output
High Speed Event Counter takes these fixed width pulses as
inputs and counts the number of such pulses
With the counting of these pulses duration of air showers can
be determined and trigger control signals can be generated
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High Speed Event Counter (HSEC) keeps the flexibility of
varying the fixed pulse widths and can measure as low as
50 nsec pulse widths
Presently, the HSEC is tuned to count pulses of 70 nsec width
HSEC has 64 channel input capability
The counting logic is implemented in an FPGA
(Spartan6-LX9) and the count value is stored temporarily in
the memory unit in the FPGA
The count values of all channels are then accessed by the
micro-controller from time to time
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The micro-controller is LPC2478 which has an ARM7-TDMI
core, which is presently among the high-end microcontrollers
The ARM7 has its own built –in Ethernet MAC containing a
fully featured 10/100 Mbps Ethernet connectivity
In the H.S.E.C. the count value accessed from the FPGA is
then encapsulated at various levels of the TCP/IP stack and
then sent over the Ethernet
The TCP/IP stack is intended to be a lite version which
implements required protocols and ensures good connectivity,
error checking and correction and flexibility in implementation
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A GUI is provided in Linux that only displays the received
count value with respect to the channels
The ARM7 micro-controller has various other communication
capabilities including UART, CAN, USB, USB-OTG, I2C and
SPI
As a flexible solution to other projects as well , these
communications are provided on the H.S.E.C.
As an example of flexibility, the USB feature can be used for
debugging errors in the program without the need to uninstall
the H.S.E.C. from the field site
L
LEVEL
CONVERSION
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The FPGA in H.S.E.C. is purposely chosen to be a high-end
FPGA so that as a future scope, the Ethernet connectivity
can be directly implemented on the FPGA itself. The
Spartan6-LX9 has sufficient resources to implement a
complete TCP/IP stack
Strong error control and correction algorithms can be
implemented on the ARM7
The ARM7 supports Linux kernel, so a board-to-board
connectivity can be implemented with slight modifications
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An embedded web-server can be implemented and stored in
the flash memory on the H.S.E.C. which will facilitate the
user to access the information about each board through any
web-browser