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Power Management for Highspeed Digital Systems Tao Zhao Electrical and Computing Engineering University of Idaho 1 Motivation Smaller CMOS process brings faster switching time and lower VDD Power integrity: voltage noise margin becomes smaller Power efficiency: static power consumption goes larger 2 How high is high-speed? Options: A. >1KHz B. >1MHz C. >1GHz It is when the passive components come in to play and even dominate the behavior of the circuits, the speed is high-speed High-speed digital system study is a study of the behavior of passive components 3 Where are the passive circuits? dI V L dt 4 Where are the passive circuits? Reduce VDD and increase VSS The problem becomes more serious when VDD goes lower Low impedance path between VDD and ground All frequencies of interest have to be covered 5 How high do we have to care? Clock frequencies Signal Rise and Fall Time 0.5 FKNEE= TRISE 6 How high do we have to care? FCLOCK=25MHz TRISE=1ns 0.5 FKNEE= TRISE =500MHz 7 Field Programmable Processing Array 32-bit reconfigurable data processor, always a slave Maximize throughput, minimize control Multiple chips can be tiled to extend the size of the data path Current revision: 250nm process, 250K gates, runs at 25MHz, radiation-hardened 16 pairs of power and ground pins Reconfigurable Memory Module Serves as memory for the FPPA Include memory address control and 1MB RAM Like the FPPA, multiple RMMs can be tiled too RMM has only been simulated in software, but not been fabricated Assume the RMM has the same DC characteristics as the FPPA The Reconfigurable Platform 10 Power Domain 11 Power Budget DC characteristic Target impedance Z t arg et VoltageSupply MaximumNoise MaximumCurrent 2.5V 5% 0.2 A 0.625 Power Delivery Path 13 Voltage Regulator Linear vs. Switching 14 Voltage Regulator Linear Voltage Regulator low efficiency low noise level cheap Switching Voltage Regulator high efficiency high noise level expensive Supply desired voltage level Supply enough current Radiation hardened 15 Wiring Impedance •Wiring Resistance is negligible •V=L*di/dt 16 Decoupling Capacitor (Decap) 17 Bulk Capacitor •ESL •Self-resonant frequency 1 FSR 2 ESL C 18 Parallel Ceramic Capacitors •Self-resonant at higher frequency •parallelism 19 Ceramic Capacitor Selection C (μF) 1 0.47 0.1 0.047 0.01 0.0047 0.001 Fsr (MHz) 5 7.3 15.9 23.2 50 73.4 159.1 Fsw (MHz) 6.3 12.4 19.9 39.2 63 124 N/A Zsw (mΩ) 102 113 111 189 174 2168 N/A 20 Ceramic Capacitor Array 21 Ceramic Capacitor Array 22 Decoupling Capacitor Network 23 Dynamic Power Management Subsystems can be powered up and down in runtime High-side load switch 24 Power-up Challenge Free from big current spike, monotonic voltage ramp-up Don’t upset the rest of the system Decoupling capacitor network adds load capacitance: internal capacitance (nF); decap (μF) Inrush current: I=C*dV/dt I=C*dv/dt=5 μF*2.5V/1 μs=12.5A 25 Soft Start-up Small dV/dt rate substantially reduces inrush current Soft start: longer time, less current The rise time of the gate voltage determines the turn-on time of the PMOS 26 Slew-rate Controllable High-side Load Switch 27 Reduce Inrush Current 28 Sequencing and Voltage Supervisor Commercial products -- ADM1066 Programmable Sequencer 10 channels for sequencing and 12 channels for supervising Contain a state machine to control the sequencing and supervising 29 Conclusion High-speed digital design focuses on the behaviors of passive circuits Digital system design trends: lower VDD requires better power integrity and power efficiency 30 Conclusion Design flow: Power budget Choose the right voltage regulator Design decoupling capacitor network to filter voltage noise Use soft-start and sequencing start-up to prevent big inrush current Voltage supervisor 31 Future Work Measurement: accurate numbers Board level interconnection: LVDS Lower voltage: Better power integrity 32 Acknowledgement Dr. Gregory Donohoe Dr. Kenneth Hass Dr. Robert Rinker All the FPPA team members 34