Transcript Slide 1
FDC Degradation Effects in A-Si:H Thin Film Transistors and Their Impact on Circuit Performance D.R. Allee, L.T. Clark, R. Shringarpure, S.M. Venugopal, Z.P. Li, and E.J. Bawolek Flexible Display Center Arizona State University Purpose • Review Degradation Mechanisms of aSi:H TFTs in Light of Recent Experiments • Highlight Similarities to NBTI • Determine Impact of Degradation on Active Matrix Backplanes • Determine Impact of Degradation on General Digital a-Si:H Circuitry • Potential Applications of Flexible a-Si:H Systems 2 Outline • Introduction • A-Si:H Thin Film Transistors • Degradation of A-Si:H TFTs – Localization of Degradation – Threshold Voltage Recovery • Impact on Circuit Performance – Degradation of Displays & Digital Logic – Circuit Simulator Incorporating Vth Shift • Similarities to NBTI • Conclusions 3 Introduction • Flexible Displays – Provide Situational Awareness – Lightweight – Rugged – Portable – Low Power – Daylight Readable SilverGirl_SS_3_16x9.wmv 4 A-Si:H TFT Performance 180C Process VGS(V) Parameter Value Yield 100% Saturation Mobility 0.8 cm2/V-s ON/OFF Ratio 2 x 108 Threshold Voltage 1.3 V Hysteresis 1.1 V Subthreshold Slope 0.58 Typical Vdd 20V 5 A-Si:H TFT Density of States • Band Tail States Energy Band-gap • Trap States Must Fill Before Significant Drain Current Acceptors Empty Acceptors Fm Full Donors EF SiNx A-Si:H EC 0≤ VG ≤ VT Free Carriers (Qn) EC EF VG > VT EF Trapped Carriers (QT) Fm EV EV Al Donors Ec EV Al Deep States Ev EC VG = VFB SiNx Extended Conduction Band States – Dangling Bonds – Amphoteric - 0,1,2 electrons – Mapped to Single Electron Density of States Band Tail States Φms • Deep States Extended Valence Band States – Weak Si-Si Bonds A-Si:H Fm qΦs Al SiNx A-Si:H 6 Degradation of A-Si:H TFTs – Creation of Defect States – Charge Injection into Gate Insulator • Threshold Voltage Rise is Proportional to – Inversion Charge – Time to ~0.3 Power • Effect is Not Small! • Shift Common to all aSi:H Processes • Shift More Severe for Low Temperature Processes 5 4 Threshold Voltage Shift (V) _ • A-Si:H TFTs Age with Voltage on the Gate • Mechanisms VGS=20V,VDS=0V 3 2 VGS=20V,VDS=10V 1 b 0 VGD= –30V,VDS=0V -1 VGD= –40V,VDS=10V -2 -3 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 Time (seconds) n EA β ΔVth t A exp t VGS ηVDS -Vth,0 . kT 7 Localization of Degradation • Channel Charge Induces Defect Creation • Linear Mode Stress Damages Entire Channel • Saturation Mode Stress Does Not Damage Near Drain • After Saturation Mode Stress – Reverse Linear IDS ‘Sees’ More Damage – Reverse Saturation IDS ‘Sees’ Less Damage Gate Nit Source Drain a-Si:H Channel (a) Linear mode stress affects channel length L Gate Nit ∆L Source a-Si:H Channel Drain (b) Saturation mode stress extent limited to L -∆L Gate Drain a-Si:H Channel Source (a) Reverse linear IDS sees all of Vth degradation Gate Drain Drain ∆L Source a-Si:H Channel (b) Reverse saturation IDS increases with VDS screening the damage at pinch-off (L-∆L) 8 Localization of Degradation • After Linear Mode Stress IDS is Identical • Damage is Uniform Throughout Channel 6.E-06 Unstressed 5.E-06 IDS (A) – In Both Linear and Saturation Regimes – For Both Forward and Reverse Configurations. 7.E-06 4.E-06 Stressed 100 s (Reverse) 3.E-06 Stressed 100 s (Forward) 2.E-06 1.E-06 Stressed 5000 s(Reverse/Forward) 0.E+00 0 5 10 15 20 VDS (V) 9 Localization of Degradation • After Saturation Mode Stress IDS is NOT Identical • Damage Must be Confined to Channel Interface. Unstressed 5.E-06 4.E-06 IDS (A) – IDS Increases Only in Saturation Regime for Reverse Configuration 6.E-06 Stressed 100 s (Reverse) 3.E-06 Stressed 100 s (Forward) 2.E-06 Stressed 5000 s (Reverse) 1.E-06 Stressed 5000 s (Forward) 0.E+00 0 5 10 15 20 VDS (V) 10 Threshold Voltage Recovery • There is an apparent recovery of threshold voltage with several hours of no applied voltages. 11 Threshold Voltage Recovery • However, the threshold voltage quickly collapses to where it would have been without rest. 12 Threshold Voltage Recovery • However, the threshold voltage quickly collapses to where it would have been without rest. • This plot removes rest time. • Degradation of 5 latches are indistinguishable. 13 Impact on Circuit Performance • Lifetime of Display Backplanes 16x8 EPD – ~10,000 hours Heat Seal connector • Lifetime of Digital Logic Source Drivers – ~ a few days! 16x8 EPD Heat Seal connector LE LE_Bar H_Bar H SR1 T5 T6 1pF 540/11 270/11 SR1_Bar Hbar_In T1 T2 540/11 270/11 1pF LE High M_Bar T5 SR1_Bar VPOS LE_Bar M SR1 T6 1pF T4 1pF 270/11 LE First stage latch / Decoder VNEG 4132/11 T9 4132/11 T10 4132/11 T11 Decoder LE_Bar L L_Bar T7 540/11 Med VCOM Low Lbar_In T3 540/11 Source Drivers 45pF Output T8 270/11 1pF Second stage latch Voltage selector Integrated a-Si:H Source Driver 14 Degradation of Digital Logic • Digital circuits must have positive static noise margin to operate. • Static noise margin eventually drops to zero with increasing threshold voltage. VDD ML OUT IN MD 15 Degradation of Digital Logic • • • Evolution of Noise Margin with Time Under Constant Gate Voltage Stress Measurements (dot), Simulations (asterix) and Analytical Equations (circle) Agree Reasonably Well Digital Circuit Lifetime Can Be Simply Expressed: VDD 2VTO T VGSL VGSD 2VTO 1 1 16 Circuit Simulator Incorporating Vth Shift 20 18 Vth degradation model tracks measured output of latch stressed for 0,1,2 and 3 hrs respectively Latch Output (V) 16 – Effect of threshold voltage shift on a 10-transistor digital latch. – NGSpice simulation results match experiment reasonably well. VDD A1 20 12 10 15 8 10 6 4 5 2 0 VDD A3 A5 0 A10 A2 A4 A6 O1 O1 A9 O2 O2 101 201 301 Time Samples (1 sample=10us) VDD A7 VOUT VIN 25 14 1 VDD 30 Vin Vin (V) • Can Now Model Circuit Performance Where Each TFT ‘Ages’ Differently A8 Age ti 401 501 ti EA n/ A exp t V V V dt GS DS t , 0 t KT i -1 t age Vt t age Aget stop t stop 17 Similarities to NBTI • • • Increased Vth (magnitude) with Gate Voltage Stress Power Law Time Dependence, ~0.25 Mechanism: Stress Induced Interface Traps – Breaking of H Passivated Dangling Si Bonds – Both H+ and H2O Proposed As Attacking Species • Some Recovery Possible with High T Anneals – But Recovery Not Thought to be Permanent • Deuterium Passivated Bonds Reduce NBTI Figure from D.K. Schroder, with permission 18 Conclusions • Degradation of a-Si:H Rooted in Fundamental Physics • Strong Similarities to NBTI • Degradation Does Not Limit Practical Lifetimes of Active Matrix Backplanes • Viability of Other Digital a-Si:H Circuits Will Depend on Specifications – Integrated Source Drivers for Displays – Flexible Active Medical Bandage • Need for Accurate Models and Simulation Tools 19