Transcript Slide 1

A Novel, Highly SEU
Tolerant Digital Circuit
Design Approach
By:
Rajesh Garg
Sunil P. Khatri
Department of Electrical and Computer Engineering,
Texas A&M University, College Station, TX
1
Outline

Background and Motivation

Previous Work

Our Approach

Experimental Results

Conclusions
2
Charge Deposition by a
Radiation Particle

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Radiation particles - protons, neutrons, alpha particles and heavy
ions
Reverse biased p-n junctions are most sensitive to particle strikes
Radiation
Charge is collected at the
Particle
drain node through drift
and diffusion
VDD
G
Results in a voltage glitch
S
D
at the drain node
_ n+
n+
Depletion
+
System state may change
Region
_+ _+ E
if this voltage glitch is
_
+ E VDD - Vjn
_
captured by at least one
+
_
memory element
_ +
+
_
 This is called SEU

May cause system failure
+
p-substrate
B
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Modeling a Radiation Particle
Strike

Charge deposited (Q) at a node is given by
Q  0.01036  L  t
where: L is the Linear Energy Transfer (MeV-cm2/mg)
t is the depth of the collection volume (mm)

A radiation particle strike is modeled by a current
pulse as
Q
t / t
iseu (t ) 
ta t b
(e  t / t a  e
b
)
where: ta is the collection time constant
tb is the ion track establishment constant

The radiation induced current always flows from ndiffusion to p-diffusion
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Motivation
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Modern VLSI Designs
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Single Event Upsets (SEUs) or Soft Errors

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Vulnerable to noise effects- crosstalk, SEU, etc
Troublesome for both memories and combinational logic
Becoming increasingly problematic even for terrestrial
designs
Applications demand reliable systems

Need to efficiently design radiation tolerant circuits

This is the focus of this talk
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Previous Approaches for
Radiation Hardening

Gate sizing is done to improve the radiation tolerance of a
design (Zhou et al.)
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SEU events are detected using built in current sensors (BICS)
(Gill et al.)
Error correction codes (Gambles et al.)
Triple modulo redundancy based approaches (Neumann et. al)
SOI devices are inherently less susceptible to radiation strikes


Higher drive capability and higher node capacitance increase
immunity to SEU
Selectively harden gates in a circuit to reduce SER by 10X
Still needs other hardening techniques to achieve SEU tolerance
Several other approaches exist to reduce the severity of
radiation particle strikes (Heijmen et al., Mohanram et al. )
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Our Approach
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Phase 1

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Gate level hardening
Phase 2
Block level hardening
 Selectively harden critical gates in a circuit

To keep area and delay overheads low
 Reduce SER by 10X

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Gate Level Hardening Approach

A radiation particle strike at a reverse biased p-n junction
results in a current flow from n-type diffusion to p-type diffusion

A gate constructed using only PMOS (NMOS) transistors cannot
experience 1 to 0 (0 to 1) upset
Radiation Particle
inp
out1p
in
out2
out2
out1
INV1
INV2
Radiation Particle
inp &
inn
out1n
inn
INV1
VDD - VTN
out1n
out1p
|VTP|
out2
INV2
Static Leakage Paths
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Our Gate Level Hardening
Approach
Low VT transistors
inp
inp
out1p
inp &
inn
out1p
VDD - VTN
X
out2
out2
out1n
out1p
out1n
|VTP|
X
out2
inn
out1n
inn
Radiation Tolerant
Inverter
Leakage currents are
lower by ~100X
Modified Inverter
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Radiation Tolerant Inverter
inp
M2
X
X
X
Radiation Particle
Strike
M8
out1p
M4
X
Radiation Particle
Strike
inp &
inn
M6
out2
out1n
out1p
X M5
out2
M3
out1n
inn
M1
X
M7
The voltage at
out2 isstrike
unaffected
A radiation particle
at any node of the
first inverter (radiation tolerant inverter) does
not affect the voltage at out2
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Radiation Tolerant Inverter
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Radiation particle strike at the outputs of INV1
Implemented using 65nm PTM with VDD=1V
Radiation strike: Q=150fC, ta=150ps & tb=38ps
inp
out1p
out2
inn
out1n
INV1
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Block Level Radiation Hardening
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100% SEU tolerance can be achieved by hardening all
gates in a circuit but this will be very costly
Protect only sensitive gates in a circuit to achieve good
SEU tolerance or coverage
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We obtain these sensitive gates using Logical Masking
PLM (G) is the probability that the voltage glitch due to a radiation
particle strike gets logically masked
PSen(G) = 1 – PLM(G)
0
For all
1
inputs
P1 = 0.5
P0 = 0.5 1

1
P1 = 0.25
0 P0 = 0.75
3
2
0→
P11= 0.5
P0 = 0.5
Radiation
Particle
1
Gate
PLM
PSen
1
0.5
0.5
2
0.75
0.25
3
0
1
If we want to protect only 2 gates then we should to protect
Gates 1 and 3 to maximize SEU tolerance
 Gate 3 is the most sensitive
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Block Level Radiation Hardening
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Obtained PSen for all gates in a circuit using a fault simulator
Sort these gates in decreasing order of their PSen
Harden gates until the required coverage is achieved
Coverage 
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G
P
 Sen
All _ hardened _ G *
G
Sen
All _ gates _ G
P
100
Coverage is a good estimate for SER reduction (Zhou et al.)
Gates at the primary output of a
circuit need to be hardened since
PSen = 1 for these gates
The dual outputs of the hardened
gates at the primary outputs drive
the dual inputs of an SEU tolerant
flip-flip (such as the flip-flop
proposed by Liu et al.)
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Critical Charge (Qcri)
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Minimum amount of
charge which can result in
an SEU event
Our hardened gates can
tolerate a large amount of
charge dumped by a
radiation particle
in
Operating frequency of
circuit determines Qcri
out1n
Qcri is the amount of
charge which results in a
voltage glitch of pulse
width T
out1p
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
CLK
out2
t1
T + t1
2T + t1
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Experimental Results
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We implemented a standard cell library L using a
65nm PTM model card with VDD = 1.0V
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Implemented both regular and hardened versions of all cell
types
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Applied our approach to several ISCAS and MCNC
benchmark circuits
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We implemented
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A tool in SIS to find the sensitive gates in a circuit
An STA tool to evaluate the delay of a hardened circuit
obtained using our approach
Layouts were created for all gates in our library for both
regular and hardened versions
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Experimental Results
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Average results over several benchmark circuits mapped
for area and delay optimality
Avg. Results
Area Mapped
Delay
Mapped
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Coverage
% Area Ovh
% Delay Ovh
90%
62.4
28.9
100%
97.7
44.3
90%
58.15
27.9
100%
96.5
47.6
Our SEU immune gates can tolerate high energy radiation
particle strikes
Critical charge is extremely high (>520fC) for all
benchmark circuits
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Suitable for space and military application because of the presence
of large number of high energy radiation particles
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Comparison Our Hardening
Approach
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Our approach is suitable for radiation
environments with high energy particles
90% Coverage
Zhou et al.
Our Approach
Area Ovh.
90%
58%
Delay Ovh.
8%
28%
Critical Charge
~150fC
>520fC
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Conclusions

SEUs are troublesome for both memories and
combinational logic


Applications demand reliable systems


Need to efficiently design radiation tolerant circuits
We developed a circuit hardening approach



Becoming increasingly problematic even for terrestrial
designs
Area overhead is ~60%
Delay overhead is ~28%
Our approach is suitable for high energy radiation
particle environments
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Critical charge is >520fC
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THANK YOU
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