Transcript Lecture 5 Multilevel Logic Synthesis

Lecture 7
Delays and Timing in Multilevel Logic
Synthesis
Hai Zhou
ECE 303
Advanced Digital Design
Spring 2002
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Outline
•
•
•
•
•
•
Gate delays
Timing waveforms
Performance calculations
Static/dynamic hazards and glitches
Designs to avoid hazards
READING: Katz 3.3, 3.4, 3.5.2, Dewey 6.5.1,
6.5.2
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Time Response in Combinational
Networks
• emphasis on timing behavior of circuits
• waveforms to visualize what is happening
• simulation to create these waveforms
• momentary change of signals at the outputs: hazards
can be useful— pulse shaping circuits
can be a problem — glitches: incorrect circuit operation
Terms:
gate delay— time for change at input to cause change at output
minimum delay vs. typical/nominal delay vs. maximum delay
careful designers design for the worst case!
rise time— time for output to transition from low to high voltage
fall time— time for output to transition from high to low voltage
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Concepts of Delays and Timing
• For a given gate, the gate delay refers to the time it
takes the output signal to respond to in input
transition
output
input
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Gate Delays
• Why is there a gate delay?
• There are actual resistances and capacitances
inside digital logic
• If you apply a unit step voltage signal to an input,
the output will not respond immediately, but after
a delay proportional to R.C
T delay = R.C
Resistance of driver
Input
Capacitance
of load
Output
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Delays in Combinational Logic
Input
transition
Output
transition
QUESTION: After the input goes from low to high
how long does it take for the output to go from low to
high (note depends on other inputs being 1 or 0)
ANSWER: Use simple delay models for each gate and
add up delays in a path from input to output
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Delays in Combinational Logic
Wire load
Capacitance C
Delay (nsec)
Low drive
High drive
Load capacitance
(pF)
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Designing Logic With High Performance
Reduce high load due to fanout
Input
transition
Higher drive gate
QUESTION: Suppose the delay from input to output is 30 nsec
and is unacceptable. How would you make a higher performance
design?
ANSWER: Reduce capacitances at various loads,
or use higher drive gates
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Gate Delays for Typical TTL Families
Delays in nano-seconds
TTL Family Maximum
tpHL
7400
15
Maximum
tpLH
22
Minimum
tpHL
7
Minimum
tpLH
11
74H00
10
10
6.2
5.9
74L00
60
60
31
35
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Gate Delay Specifications
Example gate delays in nanoseconds for LSI Logic 1.5 micron gate array
2 input AND gate.
STD LOAD 1
2
3
4
8
16
tpLH
0.7 0.8 1.0 1.2 1.8 3.2
tpHL
0.9 1.0 1.0 1.1 1.3 1.8
tpLH = Propagation delay from low to high transition at output
tpHL = Propagation delay from high to low transition at output
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Pulse Shaping Circuit
A
B
C
D
F
100
A
B
C
D
F
D remains high for
three gate delays after
A changes from low to high
F is not always 0, pulse width equals
3 gate delays
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Another Pulse Shaping Circuit
+
Resistor
A
Open
Switch
Close Switch
C
B
D
Open Switch
Initially undefined
A
B
C
D
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Hazards and Glitches
Unwanted switching at the outputs
Occur because delay paths through the circuit experience
different propagation delays
Danger if logic "makes a decision" while output is unstable
OR hazard output controls an asynchronous input (these
respond immediately to changes rather than waiting for a
synchronizing signal called a clock)
Usual solutions:
wait until signals are stable (by using a clock)
never, never, never use circuits with asynchronous inputs
design hazard-free circuits
Suggest that first two approaches be used, but we'll tell you about
hazard-free design anyway!
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Kinds of Hazards
1
1
0
Static
1-hazard
Input change causes output to go from 1 to 0 to 1
Static
0-hazard
Input change causes output to go from 0 to 1 to 0
1
0
0
1
1
0
0
1
Dynamic
1 hazards
0
Input change causes a double change
from 0 to 1 to 0 to 1 OR
from 1 to 0 to 1 to 0
0
Kinds of Hazards
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Example of a Glitch
A
AB
00
CD
A
\C
\A
D
1
G1
1
0
G3
1
\A
D
0
1
G1
F
G2
0
1
A
\C
1
1
0
1
G3
01
11
10
00
0
0
1
1
01
1
1
1
1
F
G2
0
1
D
ABCD = 1101
ABCD = 1100
C
input change within product term
11
1
1
0
0
10
0
0
0
0
B
F = A' D + A C'
A
\C
\A
D
1
G1
1
0
1
A
\C
1
G3
G2
0
ABCD = 1101
1
F
\A
D
0
G1
1
0
1
0
G3
G2
0
0
A
\C
F
\A
D
ABCD = 0101 (A is still 0)
input change that spans product terms
output changes from 1 to 0 to 1
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G1
1
1
0
G3
G2
1
1
ABCD = 0101 (A is 1)
15
1
F
Eliminating Glitches
General Strategy: add redundant terms
F = A' D + A C' becomes A' D + A C' + C' D
This eliminates 1-hazard? How about 0-hazard?
AB
00
CD
Express F in PoS form:
F = (A' + C')(A + D)
Glitch present!
A
01
11
10
00
0
0
1
1
01
1
1
1
1
D
Add term: (C' + D)
C
11
1
1
0
0
10
0
0
0
0
B
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How to design Circuits without Glitches
Theorem: Under the assumption of one input switching,
2-level SOP has no 0-hazard and POS has no 1-hazard.
Avoid 1-hazard in SOP: all adjacent 1’s are
covered by same products
F = A C' + A' D + C' D
Avoid 0-hazard in POS: all adjacent 0’s are
covered by same sums
F = (A’+C’)(A+D)(C’+D)
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Dynamic Hazards
Example with Dynamic Hazard
\A 1
B
01
\B
\C
G1
01
Slow
G3
10
G2
1
1 01
10
A
\B
G5
1 01 0
F
0
G4
10
10
V ery slow
Three different paths from B or B' to output
ABC = 000, F = 1 to ABC = 010, F = 0
different delays along the paths:
G1 slow, G4 very slow
Handling dynamic hazards very complex
Beyond our scope
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Summary
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•
•
•
•
•
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Gate delays
Timing waveforms
Performance calculations
Static/dynamic hazards and glitches
Designs to avoid hazards
NEXT LECTURE: Latches and Flip-flops
READING: Katz 6
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