Transcript Lecture 3 Two-Level Logic Minimization

Lecture 4
Combinational Logic Implementation
Technologies
Prith Banerjee
ECE C03
Advanced Digital Design
Spring 1998
ECE C03 Lecture 4
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Outline
•
•
•
•
Review of Combinational Logic Technologies
Programmable Logic Devices (PLA, PAL)
MOS Transistor Logic
READING: Katz 4.1, 4.2, Dewey 5.2, 5.3, 5.4,
5.5 5.6, 5.7, 6.2
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Programmable Arrays of Logic Gates
• Until now, we learned about designing Boolean
functions using discrete logic gates
• We will now describe a technique to arrange AND
and OR gates (or NAND and NOR gates) into a
general array structure
• Specific functions can be programmed
• Can use programmable logic arrays (PLA) or
programmable array logic (PAL)
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PALs and PLAs
Pre-fabricated building block of many AND/OR gates (or NOR, NAND)
"Personalized" by making or breaking connections among the gates
Programmable Array Block Diagram for Sum of Products Form
Inputs
Dense array of
AND gates
Product
terms
Dense array of
OR gates
Outputs
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Why PALs/PLAs Work
Equations
Example:
F0 = A + B' C'
F1 = A C' + A B
F2 = B' C' + A B
F3 = B' C + A
Personality Matrix
Product
term
AB
BC
AC
BC
A
Inputs
A B C
1 1 - 0 1
1 - 0
- 0 0
1 - -
Outputs
F0 F1 F2 F3
0 1 1 0
0 0 0 1
0 1 0 0
1 0 1 0
1 0 0 1
Key to Success: Shared Product Terms
Input Side:
1 = asserted in term
0 = negated in term
- = does not participate
Output Side:
1 = term connected to output
Reuse
0 = no connection to output
of
terms
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Example of PALs and PLAs
All possible connections are available
before programming
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Example of PALs and PLAs (Contd)
Unwanted connections are "blown"
Note: some array structures
work by making connections
rather than breaking them
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Alternative Representations
Short-hand notation
so we don't have to
draw all the wires!
Notation for implementing
F0 = A B + A' B'
F1 = C D' + C' D
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Design Example
Multiple functions of A, B, C
ABC
A
F1 = A B C
B
F2 = A + B + C
C
A
F3 = A B C
B
F4 = A + B + C
C
F5 = A xor B xor C
ABC
ABC
F6 = A xnor B xnor C
ABC
ABC
ABC
ABC
ABC
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F1
F2
F3
F4 F5
F6
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Differences Between PALs and PLAs
PAL concept — implemented by Monolithic Memories
constrained topology of the OR Array
A given column of the OR array
has access to only a subset of
the possible product terms
PLA concept — generalized topologies in AND and OR planes
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Design Example: BCD-to-Gray Code
Converter
Truth Table
K-maps
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
W
0
0
0
0
0
1
1
1
1
1
X
X
X
X
X
X
X
0
0
0
0
1
1
0
0
0
0
X
X
X
X
X
X
Y
0
0
1
1
1
1
1
1
0
0
X
X
X
X
X
X
Z
0
1
1
0
0
0
0
1
1
0
X
X
X
X
X
X
A
AB
00
01
11
10
00
0
0
X
1
01
0
1
X
1
11
0
1
X
X
10
0
1
X
X
CD
A
AB
00
01
11
10
00
0
1
X
0
01
0
1
X
0
11
0
0
X
X
10
0
0
X
X
CD
D
C
C
B
B
K-map for W
K-map for X
A
AB
A
AB
00
01
11
10
00
0
1
X
0
01
0
1
X
0
11
1
1
X
X
CD
Minimized Functions:
D
00
01
11
10
00
0
0
X
1
01
1
0
X
0
11
0
1
X
X
10
1
0
X
X
CD
D
C
W=A+BD+BC
X = B C'
Y=B+C
Z = A'B'C'D + B C D + A D' + B' C D'
D
C
10
1
1
X
X
B
B
K-map for Y
K-map for Z
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Programmed PAL
0
0
0
0
0
0
ABCD
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4 product terms per each
ORLecture
gate4
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Code Converter: Discrete Gates
A
\A
1
B
D
2
B
C
3
\A
\B
\C
D
W
B
C
D
2
A
D
B
C
22
1
1
1
X
\C
B
2
1
\B
Y
4
3
4 4
Z
5
\D
\B
C
\D
3
1: 7404 hex inverters
2,5: 7400 quad 2-input NAND
3: 7410 tri 3-input NAND
4: 7420 dual 4-input NAND
4 SSI Packages vs. 1 PLA/PAL Package!
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Another Example: Magnitude Comparator
A
AB
00
01
11
10
00
1
0
0
0
01
0
1
0
0
CD
A
AB
00
01
11
10
00
0
1
1
1
01
1
0
1
1
CD
D
11
0
0
1
ABCD
ABCD
D
0
C
ABCD
11
1
1
0
1
ABCD
10
1
1
1
0
AC
C
10
0
0
0
1
B
K-map for EQ
K-map for NE
A
AB
01
11
10
00
0
0
0
0
01
1
0
0
0
BD
A
AB
00
CD
AC
B
BD
00
01
11
10
00
0
1
1
1
01
0
0
1
1
CD
ABD
BCD
D
11
1
1
0
1
C
ABC
D
11
0
0
0
0
BCD
C
10
1
1
0
0
10
0
0
1
B
B
K-map for LT
K-map for GT
0
EQ NE LT
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Non-Gate Logic
So far we have seen:
AND-OR-Invert
PAL/PLA
Generalized Building Blocks
Beyond Simple Gates
Kinds of "Non-gate logic":
• switching circuits built from CMOS transmission gates
• multiplexer/selecter functions
• decoders
• tri-state and open collector gates
• read-only memories
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Steering Logic: Switches
Voltage Controlled Switches
Gate
Channel
Region
Oxide
Source
Drain
Silicon Bulk
n-type Si
p-type Si
"n-Channel MOS"
Metal Gate, Oxide, Silicon Sandwich
Diffusion regions: negatively charged ions driven into Si surface
Si Bulk: positively charged ions
By "pulling" electrons to the surface, a conducting channel is
formed
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Switching or Steering Logic
Voltage Controlled Switches
Gate
Source
Drain
Logic 1 on gate,
Source and Drain connected
nMOS Transistor
Gate
Source
Logic 0 on gate,
Source and Drain connected
Drain
pMOS Transistor
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Logic Gates with Steering Logic
Logic Gates from Switches
+5V
A
B
A
+5V
A
B
+5V
AB
A
A+B
Inverter
NAND Gate
NOR Gate
Pull-up network constructed from pMOS transistors
Pull-down network constructed from nMOS transistors
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Inverter with Steering Logic
Inverter Operation
+5V
"1"
+5V
"0"
"0"
Input is 1
Pull-up does not conduct
Pull-down conducts
Output connected to GND
ECE C03 Lecture 4
"1"
Input is 0
Pull-up conducts
Pull-down does not conduct
Output connected to VDD
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NAND Gate with Steering Logic
NAND Gate Operation
"1"
"0"
"1"
+5V
"1"
+5V
"0"
A = 1, B = 1
Pull-up network does not conduct
Pull-down network conducts
Output node connected to GND
ECE C03 Lecture 4
"1"
A = 0, B = 1
Pull-up network has path to VDD
Pull-down network path broken
Output node connected to VDD
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NOR Gate with Steering Logic
NOR Gate Operation
"0"
"1"
"0"
+5V
"0"
+5V
"1"
A = 0, B = 0
Pull-up network conducts
Pull-down network broken
Output node at VDD
"0"
A = 1, B = 0
Pull-up network broken
Pull-down network conducts
Output node at GND
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CMOS Transmission Gate
nMOS transistors good at passing 0's but bad at passing 1's
pMOS transistors good at passing 1's but bad at passing 0's
perfect "transmission" gate places these in parallel:
Control
Control
In
Out
Control
Switches
In
Control
Out
Control
Transistors
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In
Out
Control
Transmission or
"Butterfly" Gate
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Selection/Demultiplexing
S
Selector:
Choose I0 if S = 0
Choose I1 if S = 1
I
0
S
I
Z
S
1
S
S
Demultiplexer:
I to Z0 if S = 0
I to Z1 if S = 1
Z0
I
S
S
Z1
S
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Use of Multiplexers or Demultiplexers
A
Demultiplexers
Y
Multiplexers
B
Z
A
Y
Demultiplexers
B
Multiplexers
Z
So far, we've only seen point-to-point connections among gates
Mux/Demux used to implement multiple source/multiple destination
interconnect
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Well-formed Switching Logic
Problem with the Demux implementation:
multiple outputs, but only one connected to the input!
S
Z0
S
"0"
I
S
S
Z1
S
"0"
S
The fix: additional logic to drive every output to a known value
Never allow outputs to "float"
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Complex Steering Logic Example
N Input Tally Circuit: count # of 1's in the inputs
I
1
0
1
I1
Zero
1
0
One
0
1
I1
Straight Through
I1
"0"
Zero
One
"0"
One
"1"
Zero
Diagonal
"0"
One
Conventional Logic
for 1 Input Tally
Function
"1"
Zero
"0"
Switch Logic Implementation
of Tally Function
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Complex Steering Logic
Operation of the 1 Input Tally Circuit
"0"
"0"
One
"0"
"0"
One
"1"
Zero
"0"
"1"
Zero
"0"
Input is 0, straight through switches enabled
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Complex Steering Logic
Operation of 1 input Tally Circuit
"1"
"0"
"1"
One
Zero
"1"
"0"
One
"1"
Zero
"0"
"0"
Input = 1, diagonal switches enabled
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Complex Steering Logic Example
Extension to the 2-input case
I 1 I2
0
0
1
1
0
1
0
1
Zero One Two
1
0
0
0
0
1
1
0
0
0
0
1
I1
I2
Zero
One
Two
Conventional logic implementation
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Complex Steering Logic Example
Switch Logic Implementation: 2-input Tally Circuit
I2
I2
I1
"0"
Two
"0"
"1"
"0"
"0"
Two
One
One
Zero
Zero
"0"
I1
"0"
One
One
Cascade the 1-input implementation!
"1"
"0"
Zero
Zero
"0"
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Complex Steering Logic
Operation of 2-input implementation
"0"
"0"
"0"
"0"
"1"
"0"
"0"
One
"1"
"0"
"0"
Zero
"1"
"0"
"1"
"0"
"0"
"1"
"0"
"0"
"1"
"0"
"0"
One
Zero
"0"
"0"
"0"
One
"1"
Zero
"0"
"0"
"1"
"0"
"1"
"1"
"0"
"0"
"1"
"0"
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"0"
"1"
One
"0"
Zero
"0"
"0"
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Summary
• Review of Combinational Logic Implementation
Technologies
• Programmable Logic Devices (PLA, PAL)
• MOS Transistor Logic
• NEXT LECTURE: Combinational Logic
Implementation with Multiplexers, Decoders,
ROMS and FPGAs
• READING: Katz 4.2.2, 4.2.3, 4.2.4, 4.2.5, 10.3,
Dewey 5.7
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