Transcript MOSFET Basics - people.Virginia.EDU

MOSFET I-Vs
ECE 663
Operation of a transistor
VSG > 0
n type operation
VSG
Gate
Insulator
More
electrons
Source Channel
Substrate
Positive gate bias attracts electrons into channel
Channel now becomes more conductive
VSD
Drain
Some important equations in the
inversion regime (Depth direction)
VT = fms + 2yB + yox
Gate
Insulator
yox = Qs/Cox
Source Channel
Qs = qNAWdm
Wdm = [2eS(2yB)/qNA]
Substrate
x
VT = fms + 2yB + [4eSyBqNA]/Cox
Qinv = -Cox(VG - VT)
Drain
MOSFET Geometry
VG
Z
VD
L
S
D
z
y
x
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How to include y-dependent potential
without doing the whole problem over?
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Assume potential V(y) varies slowly along
channel, so the x-dependent and y-dependent
electrostats are independent
(GRADUAL CHANNEL APPROXIMATION)
i.e.,
Ignore ∂Ex/∂y
Potential is separable in
x and y
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How to include y-dependent potentials?
VG = yS + [2eSySqNA]/Cox
yS = 2yB + V(y)
Need VG – V(y) > VT to invert
channel at y (V increases
threshold)
Since V(y) largest at drain end, that
end reverts from inversion to
depletion first (Pinch off) 
SATURATION [VDSAT = VG – VT]
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So current:
j = qninvv = (Qinv/tinv)v
I = jA = jZtinv = ZQinvv
Qinv = -Cox[VG – VT - V(y)]
v = -meffdV(y)/dy
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So current:
I = meff ZCox[VG – VT - V(y)]dV(y)/dy
Continuity implies ∫Idy = IL
I = meff ZCox[(VG – VT )VD- VD2/2]/L
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But this current behaves like a parabola !!
I = meff ZCox[(VG – VT )VD- VD2/2]/L
ID
IDsat
VDsat
VD
We have assumed inversion in our model (ie, always above pinch-off)
So we just extend the maximum current into saturation…
Easy to check that above current is maximum for VDsat = VG - VT
Substituting, IDsat = (CoxmeffZ/2L)(VG-VT)2
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What’s Pinch off?
V0G
V0G
VG
VG
0
0
0
VD
Now add in the drain voltage to drive a current. Initially you get
an increasing current with increasing drain bias
When you reach VDsat = VG – VT, inversion is disabled at the drain
end (pinch-off), but the source end is still inverted
The charges still flow, just that you can’t draw more current
with higher drain bias, and the current saturates
Square law theory of MOSFETs
I = meff ZCox[(VG – VT )VD- VD2/2]/L,
I = meff ZCox(VG – VT )2/2L,
VD > VG - VT
J = qnv
n ~ Cox(VG – VT )
v ~ meffVD /L
VD < VG - VT
Ideal Characteristics of n-channel
enhancement mode MOSFET
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Drain current for REALLY small VD
Z
1 2

I D  m nCi  VG  VT VD  VD 
L
2


Z
I D  m nCi VG  VT VD 
L
VD  VG  VT 
Linear operation
Channel Conductance:
I D
Z
gD 
 m nCi (VG  VT )
VD V
L
G
Transconductance:
I D
Z
gm 
 m nCiVD
VG V
L
D
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In Saturation
• Channel Conductance:
ID
gD 
0
VD V
G
• Transconductance:
I D sat 
gm 
Z
2
m nCi VG  VT 
2L
I D
Z
 m nCi VG  VT 
VG V
L
D
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Equivalent Circuit – Low Frequency AC
• Gate looks like open circuit
• S-D output stage looks like current source with channel
conductance
ID
ID
ID 
VD 
VG
VD V
VG V
G
D
i  g D v d  g mv g
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Equivalent Circuit – Higher Frequency AC
• Input stage looks like capacitances gate-to-source(gate) and
gate-to-drain(overlap)
• Output capacitances ignored -drain-to-source capacitance
small
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Equivalent Circuit – Higher Frequency AC
• Input circuit:
i in  jCgs  Cgd v g  j 2fCgatev g
• Input capacitance is mainly gate capacitance
• Output circuit:
i out  g mv g
i out
gm

i in
2fCgate
I D
Z
gm 
 m nCiVD
VG V
L
D
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Maximum Frequency (not in saturation)
• Ci is capacitance per unit area and Cgate is total capacitance
of the gate
Cgate  Ci ZL
• F=fmax when gain=1 (iout/iin=1)
fmax
gm

2Cgate
fmax
Z
m nVDCi
m nVD
L


2Ci ZL 2L2
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Maximum Frequency (not in saturation)
f max 
max
m nVD
2L2
1

L/v
v  mVD / L
(Inverse transit time)
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Switching Speed, Power Dissipation
ton = CoxZLVD/ION
Trade-off: If Cox too small, Cs and Cd take over and you lose
control of the channel potential (e.g. saturation)
(DRAIN-INDUCED BARRIER LOWERING/DIBL)
If Cox increases, you want to make sure you don’t control
immobile charges (parasitics) which do not contribute to
current.
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Switching Speed, Power Dissipation
Pdyn = ½ CoxZLVD2f
Pst = IoffVD
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CMOS
NOT gate
(inverter)
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CMOS
Vin = 1
Vout = 0
NOT gate
(inverter)
Positive gate turns nMOS on
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CMOS
Vin = 0
Vout = 1
NOT gate
(inverter)
Negative gate turns pMOS on
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So what?
• If we can create a NOT gate
we can create other gates
(e.g. NAND, EXOR)
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So what?
Ring Oscillator
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So what?
• More importantly, since one is open and one is shut at steady
state, no current except during turn-on/turn-off
 Low power dissipation
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Getting the inverter output
ON
Gain
OFF
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ID
gD 
0
VD V
G
gm 
I D
Z
 m nCi VG  VT 
VG V
L
D
What’s the gain here?
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Signal Restoration
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BJT vs MOSFET
• RTL logic vs CMOS logic
• DC Input impedance of MOSFET (at gate end) is infinite
Thus, current output can drive many inputs  FANOUT
• CMOS static dissipation is low!!
~ IOFFVDD
• Normally BJTs have higher transconductance/current (faster!)
IC = (qni2Dn/WBND)exp(qVBE/kT)
gm = IC/VBE = IC/(kT/q)
ID = mCoxW(VG-VT) 2/L
gm = ID/VG = ID/[(VG-VT)/2]
• Today’s MOSFET ID >> IC due to near ballistic operation
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What if it isn’t ideal?
• If work function differences and oxide charges are present,
threshold voltage is shifted just like for MOS capacitor:
VT  VFB
2e s qN A (2y B )
 2y B 
Ci
2e s qNA (2y B )

Qf 
  fms    2y B 
Ci 
Ci

• If the substrate is biased wrt the Source (VBS) the
threshold voltage is also shifted
VT  VFB
2e s qNA (2y B  VBS )
 2y B 
Ci
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Threshold Voltage Control
• Substrate Bias:
VT  VFB
2e s qNA (2y B  VBS )
 2y B 
Ci
VT  VT (VBS )  VT (VBS  0)
2e s qNA
VT 
Ci

2y B  VBS  2y B 
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Threshold Voltage Control-substrate bias
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It also affects the I-V
VG
The threshold voltage is increased due to the depletion region
that grows at the drain end because the inversion layer shrinks
there and can’t screen it any more. (Wd > Wdm)
Qinv = -Cox[VG-VT(y)], I = -meffZQinvdV(y)/dy
VT(y) = y + √2esqNAy/Cox
y = 2yB + V(y)
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It also affects the I-V
IL = ∫meffZCox[VG – (2yB+V) - √2esqNA(2yB+V)/Cox]dV
I = (ZmeffCox/L)[(VG–2yB)VD –VD2/2
-2√2esqNA{(2yB+VD)3/2-(2yB)3/2}/3Cox]
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We can approximately include this…
Include an additional charge term from the
depletion layer capacitance controlling V(y)
Q = -Cox[VG-VT]+(Cox + Cd)V(y)
where Cd = es/Wdm
Q = -Cox[VG –VT - MV(y)], M = 1 + Cd/Cox
ID = (ZmeffCox/L)[(VG-VT - MVD/2)VD]
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Comparison between different models
Square Law Theory
Bulk Charge Theory
Body Coefficient
Still not good below threshold or above saturation
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Mobility
• Drain current model assumed constant mobility in channel
• Mobility of channel less than bulk – surface scattering
• Mobility depends on gate voltage – carriers in inversion
channel are attracted to gate – increased surface scattering
– reduced mobility
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Mobility dependence on gate voltage
m0
m
1  (VG  VT )
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Sub-Threshold Behavior
• For gate voltage less than the threshold – weak inversion
• Diffusion is dominant current mechanism (not drift)
n
n(o)  n(L)
ID  JD A  qADn
 qADn
y
L
n(0)  ni e
q ( y s y B ) / kT
n(L)  ni e
q ( y s y B VD ) / kT
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Sub-threshold
qADn ni e
ID 
L
yB / kT
1  e
qVD / kT
e
qys / kT
We can approximate ys with VG-VT below threshold since all
voltage drops across depletion region
qADn ni e y
ID 
L
B
/ kT
1  e
qVD / kT
e
q VG VT  / kT
•Sub-threshold current is exponential function of applied gate voltage
•Sub-threshold current gets larger for smaller gates (L)
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Subthreshold Characteristic
Subthreshold Swing
S
1
log ID  VG 
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Much of new research depends on reducing S !
Tunneling transistor
– Band filter like operation
Ghosh, Rakshit, Datta
(Nanoletters, 2004)
(Sconf)min=2.3(kBT/e).(etox/m)
Hodgkin and Huxley, J. Physiol. 116, 449 (1952a)
J Appenzeller et al, PRL ‘04
Subthreshold slope = (60/Z) mV/decade
Much of new research depends on reducing S !
• Increase ‘q’ by collective motion (e.g. relay)
Ghosh, Rakshit, Datta, NL ‘03
• Effectively reduce N through interactions
Salahuddin, Datta
• Negative capacitance
Salahuddin, Datta
• Non-thermionic switching (T-independent)
Appenzeller et al, PRL
• Nonequilibrium switching
Li, Ghosh, Stan
• Impact Ionization
Plummer
More complete model – sub-threshold to
saturation
• Must include diffusion and drift currents
• Still use gradual channel approximation
• Yields sub-threshold and saturation behavior for long
channel MOSFETS
• Exact Charge Model – numerical integration
Z esm n
ID 

L LD 0 y
VD y s
B
e
y V

np0 

F  y,V ,

p
p0 

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Exact Charge Model (Pao-Sah)
– Long Channel MOSFET
http://www.nsti.org/Nanotech2006/WCM2006/WCM2006-BJie.pdf
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