Transcript MOS Fundamentals

MOSFETs
ECE 663
A little bit of history..
ECE 663
Operation of a transistor
VSG > 0
n type operation
VSG
Gate
Insulator
More
electrons
Source Channel
Substrate
Positive gate bias attracts electrons into channel
Channel now becomes more conductive
VSD
Drain
Operation of a transistor
VSG
Gate
Insulator
Source
Channel
VSD
Drain
Substrate
Transistor turns on at high gate voltage
Transistor current saturates at high drain bias
Start with a MOS capacitor
VSG
Gate
Insulator
Source Channel
Substrate
VSD
Drain
MIS Diode (MOS capacitor) – Ideal
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Questions
What is the MOS capacitance? QS(yS)
W
What are the local conditions during inversion?
How does the potential vary with position?
yS,cr
y(x)
How much inversion charge is generated at the surface? Qinv(x,yS)
Add in the oxide: how does the voltage divide?
yS(VG), yox(VG)
How much gate voltage do you need to invert the channel? VTH
How much inversion charge is generated by the gate? Qinv(VG)
What’s the overall C-V of the MOSFET?
QS(VG)
Ideal MIS Diode n-type, Vappl=0
Assume Flat-band
at equilibrium
qfS
EC
EF
Ei
EV
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Ideal MIS Diode n-type, Vappl=0
fms
Eg


 fm    
 yB   0
2q


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Ideal MIS Diode p-type, Vappl=0
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Ideal MIS Diode p-type, Vappl=0
fms
Eg


 fm    
 yB   0
2q


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Accumulation
Pulling in majority carriers at surface
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But this increases the barrier
for current flow !!
n+
p
n+
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Depletion
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Inversion
yB
Need CB to dip below EF.
Once below by yB, minority carrier density trumps the intrinsic density.
Once below by 2yB, it trumps the major carrier density (doping) !
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Sometimes maths can help…
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P-type semiconductor Vappl0
Convention for p-type: y positive if bands bend down
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Ideal MIS diode – p-type
n p  ni e
( Ei' EF ) / kT
 ni e ( E qyE
i
F
) / kT
 n p 0e qy / kT  n p 0e y
CB moves towards EF if y > 0  n increases
pp  pp0e qy / kT  pp0e y
VB moves away from EF if y > 0  p decreases
q

kT
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Ideal MIS diode – p-type
At the semiconductor surface, y = ys
ns  np 0e y
s
ps  pp 0e y
s
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Surface carrier concentration
ns  np 0e
ys
ps  p p 0 e
ys
• ys < 0 - accumulation of holes
EC
EF
• ys =0 - flat band
• yB> ys >0 – depletion of holes
• ys =yB - intrinsic concentration ns=ps=ni
• ys > yB – Inversion (more electrons than holes)
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Want to find y, E-field, Capacitance
• Solve Poisson’s equation to get E field, potential based on
charge density distribution(one dimension)
dE
  E   / k 0   /  s 
 1 D
dx
dy
E  
dx
d 2y

  /  s
2
dx
( x)  q(ND  NA  pp  np )
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• Away from the surface,  = 0
 ND  NA  np0  pp0
• and
pp  np  pp0e y  np0ey
d 2y
q
 2   pp 0 (e y  1)  n p 0 (e y  1)
s
dx
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Solve Poisson’s equation:
d 2y
q
 2   pp 0 (e y  1)  n p 0 (e y  1)
s
dx
E = -dy/dx
d2y/dx2 = -dE/dx
= (dE/dy).(-dy/dx)
= EdE/dy
d 2y
q
EdE/dy
 2   pp 0 (e y  1)  n p 0 (e y  1)
s
dx
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Solve Poisson’s equation:
• Do the integral:
• LHS:
x2
dy
x
 xdx 
2
dx
0
x
• RHS:
x
e
0
 x
x
dx,  dx
0
• Get expression for E field (dy/dx):
n p 0 y

 kT   qpp 0   y
e  y  1

 e  y  1 
 
pp0
 q   2 s  

2
E
2
field
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Define:
LD 
kT s
s

2
qpp 0
pp 0q
Debye Length

n p 0   y
n p 0 y



e  y  1
F  y,
 e  y  1 

pp0  
pp0


Then:
1
2
E>0
Efield
np0 
2kT 


F  y,
qLD 
p p 0 
+ for y > 0 and – for y < 0
y>0
E<0
y<0
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Use Gauss’ Law to find
surface charge per unit
area
np0 
2kT 


Qs   s ES  
F  y s ,
qLD 
pp 0 
2kT
Qs  
qLD
 y
 e  y s  1  npp0 ey  y s  1
p0


S
1
2
s
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Accumulation to depletion to strong Inversion
• For negative y, first term in F dominates – exponential
• For small positive y, second term in F dominates - y
• As y gets larger,
n p 0e y
1
pp0
second exponential gets big
yB = (kT/q)ln(NA/ni) = (1/)ln(pp0/√pp0np0)
(np0/pp0) = e-2yB
yS > 2yB
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Questions
 What is the MOS capacitance? QS(yS)
 What are the local conditions during inversion?
How does the potential vary with position?
yS,cr
y(x)
How much inversion charge is generated at the surface? Qinv(x,yS)
Add in the oxide: how does the voltage divide?
yS(VG), yox(VG)
How much gate voltage do you need to invert the channel? VTH
How much inversion charge is generated by the gate? Qinv(VG)
What’s the overall C-V of the MOSFET?
QS(VG)
Charges, fields, and potentials
• Charge on metal = induced surface charge in semiconductor
• No charge/current in insulator (ideal)
metal
insul semiconductor
depletion
inversion
QM  Qn  qNAW  QS
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Charges, fields, and potentials
Electric Field
Electrostatic Potential
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Depletion Region
Electric Field
Electrostatic Potential
n p 0 y

 kT   qpp 0   y
e  y  1

 e  y  1 
 
pp0
 q   2 s  

2
E
2
field
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Depletion Region
Electric Field
Electrostatic Potential
y = ys(1-x/W)2
Wmax = 2s(2yB)/qNA
yB = (kT/q)ln(NA/ni)
ECE 663
Questions
 What is the MOS capacitance? QS(yS)
 What are the local conditions during inversion?
 How does the potential vary with position?
yS,cr
y(x)
How much inversion charge is generated at the surface? Qinv(x,yS)
Add in the oxide: how does the voltage divide?
yS(VG), yox(VG)
How much gate voltage do you need to invert the channel? VTH
How much inversion charge is generated by the gate? Qinv(VG)
What’s the overall C-V of the MOSFET?
QS(VG)
Couldn’t we just solve
this exactly?
Exact Solution
U = y
US = yS
UB = yB
dy/dx = -(2kT/qLD)F(yB,np0/pp0)
U
 dU/F(U) =  x/L
D

US
F(U) = [eUB(e-U-1+U)-e-UB (eU-1-U)]1/2
Exact Solution
 = qni[eUB(e-U-1) – e-UB(eU-1)]
US
 dU’/F(U’,U ) =  x/L
B
D

U
F(U,UB) = [eUB(e-U-1+U) + e-UB (eU-1-U)]1/2
Exact Solution
NA = 1.67 x 1015
Qinv ~ 1/(x+x0)a
x0 ~ LD . factor
Questions
 What is the MOS capacitance? QS(yS)
 What are the local conditions during inversion?
 How does the potential vary with position?
yS,cr
y(x)
 How much inversion charge is generated at the surface? Qinv(x,yS)
Add in the oxide: how does the voltage divide?
yS(VG), yox(VG)
How much gate voltage do you need to invert the channel? VTH
How much inversion charge is generated by the gate? Qinv(VG)
What’s the overall C-V of the MOSFET?
QS(VG)
Threshold Voltage for Strong Inversion
• Total voltage across MOS structure= voltage across
dielectric plus ys
QS
VT (strong _ inversion)  Vi  yS 
 2y B
Ci
QS (SI )  qN AWmax  qN A
2 s y s (inv )
 2 s qN A (2y B )
qN A
2 s qN A (2y B )
 VT 
 2y B
Ci
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Notice Boundary Condition !!
oxVi/tox = sys/(W/2) Before Inversion
After inversion there is a discontinuity in D due to surface Qinv
Vox (at threshold) = s(2yB)/(Wmax/2)Ci =
2 s qN A (2y B )
 VT 
 2y B
Ci
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Local Potential vs Gate voltage
VG = Vfb + ys + (kstox/kox)√(2kTNA/0ks)[ys + eys-2yB)]1/2
yox
ys
Initially, all voltage drops across channel (blue curve). Above threshold,
channel potential stays pinned to 2yB, varying only logarithmically, so that
most of the gate voltage drops across the oxide (red curve).
Look at Effective charge width
~Wdm/2
~tinv
Initially, a fast increasing channel potential drops across
increasing depletion width
Eventually, a constant potential drops across a decreasing
inversion layer width, so field keeps increasing and thus
matches increasing field in oxide
Questions
 What is the MOS capacitance? QS(yS)
 What are the local conditions during inversion?
 How does the potential vary with position?
yS,cr
y(x)
 How much inversion charge is generated at the surface? Qinv(x,yS)
 Add in the oxide: how does the voltage divide?
yS(VG), yox(VG)
 How much gate voltage do you need to invert the channel? VTH
How much inversion charge is generated by the gate? Qinv(VG)
What’s the overall C-V of the MOSFET?
QS(VG)
Charge vs Local Potential
Qs ≈ √(20kskTNA)[ys + eys-2yB)]1/2
Beyond threshold, all charge goes to inversion layer
How do we get the curvatures?
Add other terms and keep
Leading term
EXACT
Inversion Charge vs Gate voltage
Q ~ eys-2yB), ys- 2yB ~ log(VG-VT)
Exponent of a logarithm gives a linear variation of Qinv with VG
Qinv = -Cox(VG-VT)
Why Cox?
Questions
 What is the MOS capacitance? QS(yS)
 What are the local conditions during inversion?
 How does the potential vary with position?
yS,cr
y(x)
 How much inversion charge is generated at the surface? Qinv(x,yS)
 Add in the oxide: how does the voltage divide?
yS(VG), yox(VG)
 How much gate voltage do you need to invert the channel? VTH
 How much inversion charge is generated by the gate? Qinv(VG)
What’s the overall C-V of the MOSFET?
QS(VG)
Capacitance


 np0
 y
y

1

e

e

1




p
QS
S 
p0 

CD 

y
2LD

np0 

F  y S ,

p
p0 

s
s
For ys=0 (Flat Band):
2
3
x
x
x

 ........
Expand exponentials….. e  1  x 
2! 3!
S
CD (flat _ band ) 
LD
ECE 663
Capacitance of whole structure
• Two capacitors in series:
Ci - insulator
CD - Depletion
1 1
1


C Ci CD
OR
i
Ci 
d
Ci CD
C
Ci  CD
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Capacitance vs Voltage
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Flat Band Capacitance
• Negative voltage = accumulation – C~Ci
• Zero voltage – Flat Band
V  0  y  0  C  CFB
i
d  LD
s
1
1
1
1
1  s d   i LD


 


CFB Ci CD  i  s
i s
i
d LD
 CFB
i

d   LD
i
s
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CV
• As voltage is increased, C goes through minimum
(weak inversion) where dy/dQ is fairly flat
• C will increase with onset of strong inversion
• Capacitance is an AC measurement
• Only increases when AC period long wrt minority
carrier lifetime
• At “high” frequency, carriers can’t keep up – don’t
see increased capacitance with voltage
• For Si MOS, “high” frequency = 10-100 Hz
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CV Curves – Ideal MOS Capacitor
'
min
C
i

d   Wmax
i
s
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But how can we operate gate at
today’s clock frequency (~ 2 GHz!)
if we can’t generate minority
carriers fast enough (> 100 Hz) ?
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MOScap vs MOSFET
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MOScap vs MOSFET
Gate
Insulator
Channel
Substrate
Minority carriers generated by
RG, over minority carrier lifetime
~ 100ms
So Cinv can be << Cox if fast gate
switching (~ GHz)
Gate
Insulator
Source
Channel
Drain
Substrate
Majority carriers pulled in
from contacts (fast !!)
Cinv = Cox
ECE 663
Example Metal-SiO2-Si
•
•
•
•
Wmax
NA = 1017/cm3
At room temp kT/q = 0.026V
ni = 9.65x109/cm3
s = 11.9x1.85x10-14 F/cm
N 
4 s kT ln A 
11.9 x8.85 x10 14 X 0.026 ln1017 9.65 x109 
ni 



1.6 x10 19 X 1017
2
q NA
Wmax  10 5 cm  0.1mm
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Example Metal-SiO2-Si
• d=50 nm thick oxide=10-5 cm
• i=3.9x8.85x10-14 F/cm
 i 3.9 x8.85 x10 14
Ci  
 6.9 x10 7 F / cm 2
5
d
10
 1017 
2kT  N A 
y s (inv )  2y B 
ln
  0.84Volts
  2 x0.026x ln
9
q
n
9
.
65
x
10
 i 


C
'
min
i
3.9 x8.85 x10 14
8
2



9
.
1
x
10
F
/
cm
d   Wmax 5 x10 7  3.9 11.910 5
i
s
'
Cmin
 0.13
Ci
VTH
qN AWmax
1.6 x10 19 x1017 x10 5

 2y B 
 y s (inv )  0.23  0.84  1.07Volts
7
Ci
6.9 x10
ECE 663
Real MIS Diode: Metal(poly)-Si-SiO2 MOS
• Work functions of gate and semiconductor are
NOT the same
• Oxides are not perfect
– Trapped, interface, mobile charges
– Tunneling
• All of these will effect the CV characteristic and
threshold voltage
ECE 663
Band bending due to work function difference
VFB  fms
ECE 663
Work Function Difference
• qfs=semiconductor work function =
difference between vacuum and Fermi level
• qfm=metal work function
• qfms=(qfm- qfs)
• For Al, qfm=4.1 eV
• n+ polysilicon qfs=4.05 eV
• p+ polysilicon qfs=5.05 eV
• qfms varies over a wide range depending on
doping
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SiO2-Si Interface Charges
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Standard nomenclature for Oxide charges:
QM=Mobile charges (Na+/K+) – can cause
unstable threshold shifts – cleanliness
has eliminated this issue
QOT=Oxide trapped charge – Can be anywhere
in the oxide layer. Caused by broken
Si-O bonds – caused by radiation damage
e.g. alpha particles, plasma processes,
hot carriers, EPROM
ECE 663
QF= Fixed oxide charge – positive charge layer
near (~2mm) Caused by incomplete
oxidation of Si atoms(dangling bonds)
Does not change with applied voltage
QIT=Interface trapped charge. Similar in origin
to QF but at interface. Can be pos, neg,
or neutral. Traps e- and h during device
operation. Density of QIT and QF usually
correlated-similar mechanisms. Cure
is H anneal at the end of the process.
Oxide charges measured with C-V methods
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Effect of Fixed Oxide Charges
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Surface Recombination
Lattice periodicity broken at surface/interface – mid-gap E levels
Carriers generated-recombined per unit area
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Interface Trapped Charge - QIT
• Surface states – R-G centers caused by disruption of lattice
periodicity at surface
• Trap levels distributed in band gap, with Fermi-type distributed:
ND
1

N D 1  g D e ( E
F
ED ) / kT
• Ionization and polarity will depend on applied voltage (above or
below Fermi level
• Frequency dependent capacitance due to surface recombination
lifetime compared with measurement frequency
• Effect is to distort CV curve depending on frequency
• Can be passivated w/H anneal – 1010/cm2 in Si/SiO2 system
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Effect of Interface trapped charge on C-V curve
ECE 663
a – ideal
b – lateral shift – Q oxide, fms
c – distorted by QIT
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Non-Ideal MOS capacitor C-V curves
• Work function difference and oxide charges shift CV curve in
voltage from ideal case
• CV shift changes threshold voltage
• Mobile ionic charges can change threshold voltage as a function of
time – reliability problems
• Interface Trapped Charge distorts CV curve – frequency
dependent capacitance
• Interface state density can be reduced by H annealing in Si-Si02
• Other gate insulator materials tend to have much higher
interface state densities
ECE 663
All of the above….
• For the three types of oxide charges the CV curve is shifted
by the voltage on the capacitor Q/C
VFBoxide_ ch arg e
 1 1 d


x

(
x
)
dx


Ci  d 0
• When work function differences and oxide charges are
present, the flat band voltage shift is:
VFB  fms

Qf

 Qm  Qot 
Ci
ECE 663
Some important equations in the
inversion regime (Depth direction)
VT = fms + 2yB + yox
yox = Qs/Cox
Gate
Insulator
Source Channel
Qs = qNAWdm
Wdm = [2S(2yB)/qNA]
Drain
Substrate
x
VT = fms + 2yB + ([4SyBqNA] - Qf + Qm + Qot)/Cox
Qinv = Cox(VG - VT)