Transcript Transistor and Circuit Design Optimization for Low

Transistor and Circuit Design Optimization
for Low-Power CMOS
By M.Chang, C.Chang,C.Chao,K.Goto,M.Leong,L.Lu,and
C.Diaz
Presented By:
Mozammel Haque
For the Low-Power High-Sped VLSI
ELEC 5705Y
W-2009
Contents
￭ Introduction
￭ Low power techniques
￭ Procedures/Discussion
• Transistor Scaling
• Circuit Design techniques for static leakage and
active-power management
￭ Conclusion
￭ References
Introduction
￭ Transistor scaling has been a highly successful method for
Silicon technology
￭ CMOS technology scaling has now moved to a power
constrained condition.
￭ Circuit techniques to reduce chip standby leakage has
become a key enabler
￭ Scaling is a trading off performance and leakage
￭ Different circuit design techniques to optimize the delay and
leakage are discussed in this paper.
￭ Along with continued scaling, hybrid materials and new
process technologies are also recent research interest to
balance leakage and delay.
Low Power Techniques
￭ General Good Design Practices
￭ Transistor sizing
￭ Process shrink
￭ Voltage scaling
￭ Clock gating/transition reduction
￭ Power down testability blocks when not in the test mode
￭ Power down the functional blocks
￭ Minimize sequential elements
￭ Downsize all non-critical path circuits
￭ Reduce loading on the clock
￭ Parallelism
￭ Adiabatic circuits
Discussions
1 Transistor Scaling
A.
B.
C.
Power Supply Voltage & Gate-Oxide Thickness
Drive Current and Performance
Structural and Material Fundamental Limits and
Implications
2. Circuit Design for Leakage - and Active-Power Management
A.
B.
C.
D.
E.
F.
G.
Active-Power management
Leakage-Power management
Multi-Vt Transistors
Power-Supply Voltage Scaling
Transistor Stacking and Power-supply Gating
Dynamic Body Biasing
Non-minimum Channel Length
1.
Transistor Scaling
A. Power Supply Voltage & Gate-Oxide Thickness:
￭
VDD was kept constant at 5V from 2 -um to 0.5- um technology
• Continued geometrical scaling resulted very high electric field, power
dissipation, raised performance concerns.
￭
VDD and Vt tend to scale by same factor to limit drive-current
degradation
• But Vt scaling results in an exponential increase of the OFF-state leakage
and therefore standby power. As a result,
￭
Technology scaling has driven in an increase of the gatedielectric nominal operating fields.
￭
Exponential increasing of gate tunneling current has prevented
any significant gate-dielectric scaling since 90-nm node.
Transistor Scaling Cont…
Power-supply scaling, operating electric-field,and Current trends as a
function of tox:
B. Drive Current and Performance
For digital applications, higher Id and lower C
Are the key factors for CMOS circuit performance
Current (Id) factor:
￭ High performance demand has driven Idsat to
increase in each generation
• through Vt scaling
• mobility enhancement techniques (channel
orientation, strained –silicon technique)
￭ In traditional CMOS inverter delay model,
Idsat is overly optimistic which causes the delay
lower. This is not accurate to project circuit
performance.
￭ Instead of Idsat, an effective current Ideff is
proposed which is more appropriate during
switching of an inverter . The expected ratio
of Ideff/Idsat is approx. 0.6. Ideff considers
the relevance of SCE control as well as Vdd,Vt
scaling
 
I dsat
CV
I dsat
K n /W

(VGS  VT )2 (1  VDS )
2L
IH  IL
2
 I ds , (Vgs=Vdd, Vds=Vdd /2)
I eff 
IH
I L  Ids, (Vgs=Vdd/2,Vds=Vdd)
Ideff  Coc,invW ((3   )Vdd / 4  Vt )
 =Cl*Vdd(1/Ideff,n+1/Ideff,p)
Current factor Cont…
The inverter gate-delay trend projections in conventional Idsat model and
new Ideff approach.
￭ The approach of Ideff
accurately captures the delay
behavior of nontraditionally scaled
devices, where mobility
and Vt/ Vdd are scaled in
neither a regular nor
uniform manner.
￭ It reflects well the slow
down on speed scaling of
a conventional CMOS.
Fig.2. The inverter gate-delay trend projections in
conventional Idst model and new Ideff approach
Capacitance factor:
￭ Capacitance is another important factor
for CMOS speed.
CTotal  CG  C parasitic
CG  CGC  2COV
￭ Gate-length scaling will continue
reduction on CG but not on Cparasitic.
￭ Scaling of Ctotal is not warranted due to
non-scaling parasitic capacitance.
￭ For the 32-nm node and beyond,
breakthroughs will be required to
continue capacitance scaling trend to
sustain/maximize performance
improvement as well as the reduction
of the intrinsic active power per unit
speed.
Fig. Capacitance scaling trend
C. Structural and Material Fundamental Limits and
Implications
￭ Scaling for 22-nm and beyond, the control of channel sub-threshold leakage has
become a very challenging task.
￭ When oxide thickness was scaled down to ~1.5nm, standby and active power
increases.
￭ The use of high-k/MG dielectric can help to scale the electrical oxide
thickness(EOT) without reduction of physical dielectric thickness.
￭ Choice of such materials is the high research interest in CMOS technology
￭ To slow down the scaling of EOT and Vdd novel substrates/or stressors used
￭ Hybrid –orientation is studied.
￭ SiGe,GePMOS,GaAs, InGaAs have been proposed
￭ Ultrathin body or multigate devices may be needed
￭ High mobility channel material is another option.
2.
Circuit Design for Leakage - and Active-Power
Management
A.
B.
C.
D.
E.
F.
G.
Active-Power management
Leakage-Power management
Multi-Vt Transistors
Power-Supply Voltage Scaling
Transistor Stacking and Power-supply Gating
Dynamic Body Biasing
Non-minimum Channel Length
A. Active-Power Management
￭ Total power dissipation
•
Active power ( for switching)
•
Direct path/Short circuit ( ramp input)
•
Static power
•
DC power
•
Sub-threshold leakage
Pactive   CfV 2
￭ In CMOS ,Active power dissipation is more dominant resulting from charging
and discharging capacitances during function evaluation by the circuit blocks.
￭ Active-power can be reduced by the following techniques:
• Dynamic frequency-scaling(DFS)
Pactive ( DFS )   Cf (t )V 2
Lower performance: lower f
Higher performance: higher f
• Dynamic voltage-scaling(DVS)
Pactive (DVS )  Cf (t )V 2 (t )
Lower performance: lower V
Higher performance: higher V, Circuit functionality must be checked
Active-Power Management Contd..
• Circuit-Partitioning:
• Dividing the circuit into smaller blocks
• Exploring the criticality of the block timing
• Raising the power-supply voltage for critical blocks
• Lowering the power-supply voltage for non-critical blocks.
Pactive  i i Ci fVi 2
• Due to different power-supply voltage the signal swing would be
different as well.So,
• Level shifters should be added between these blocks to ensue that
proper signaling is carried out.
Disadvantages:
• The power grid becomes more complicated
• Additional good-resolution voltage regulator is required
• Balancing performance and power is also critical.
B.
Leakage-Power Management
Leakage power, Pleakage is the static power consumption when circuit is not
switching.
Pleakage   Nt , where Nt : number of transistors
 : approximation cons tan t
￭ Leakage current is a function of Vt, Vds (Vgs=0), input state,input registers
￭ It’s dominated by sub-threshold current
￭ With a large number of inputs and registers, it is rather difficult to
approximate leakage power.
￭ Finding the maximum and minimum bounds of the leakage power is nondeterministic polynomial-time.
￭ Input Vector Controls (IVC) can be exploited to minimize the leakage current.
￭ Given a state with higher probability to occur,circuit can be designed to
minimize leakage power. It could be done with proper gate-input-ordering.
C.
￭
￭
Multi-Vt Transistors
Sub-threshold current strongly depends on Vt. So,
Different Vt transistors can be used for performance and leakage-power tradeoff.
• For lower leakage current but
lower performance( more delay)
: Gates with high Vt transistors
• For higher performance( less delay) : Gates with low Vt transistors
but larger leakage current ,critical path.
￭
For dual Vt transistors leakage power reduction can be reformulated as
P / leakage   L N L   H N H (dual Vt ), Pleakage   Nt (sin gle Vt )
Leakage  power reduction :
P / leakage / Pleakage  ( L N L   H N H ) /  Nt  ( L /  )( N L / Nt )  (  H /  )( N H / Nt )
 I off , L / I off ,t ( N L / Nt  ( Ioff ,H / I off ,L ) N H / Nt )
￭
￭
For top critical path, more low Vt transistors should be used but it will contribute to
leakage-power
For lowering leakage-power high Vt transistors should be used
Multi-Vt Transistors cont…..
￭ Placing a medium third Vt transistor between the low-Vt and high-Vt
device can enable further leakage - power reduction. For 3- Vt transistors
leakage power reduction is
P//leakage / Pleakage  NL / Nt  (Ioff ,M / Ioff ,L )(NM / Nt )  (Ioff ,H / Ioff ,L )(NH / Nt )
￭ Low –Vt transistors NL should be smaller than the dual - Vt transistors
approach in order to see a further leakage-power reduction.
￭ Its seen that multiple Vt’s can attain
a greater leakage-power reduction
while minimizing the circuit area,
and at the same time meeting the
performance goal.
D.
Power-Supply Voltage Scaling
￭ Power-supply –voltage scaling is effective in reducing both
• Active-power
• Leakage power
￭ DVS(dynamic voltage scaling) approach would help to achieve the goals.
￭ Supply-voltage lower limit (Vccmin) is dictated by functionality of the circuit.
￭ Example Dual power-supply SRAM
• Vdd_bit for bit –cell array
• Vdd_core for peripheral /core logic.
• Vdd_bit is fixed at regular voltage
• Vdd_core can be lower to reduce
dynamic power
• Power reduction by 20%-40%
E. Power-supply Gating
￭ To reduce standby-leakage, power gating by header/footer is a popular method
where all parts of circuit are not functioning all the time, and nonfunctioning parts
can be turned off. Footer/header can be controlled by a sleep signal
￭ Two types of power gating:
• Coarse-grain: Turning off a footer/header would turn off a block of circuit.
• small area overhead, larger leakage reduction
• Fine-grain : Turning off a footer/header would turn off a single gate
• faster wake-up time
Fig. Fine grain
Fig. Coarse-grain
Power-supply Gating cont….
￭ To further reduce the leakage for coarse-grain header/footer
• Source biasing or reduced power –supply voltage in standby mode can be
applied
• During switching, there would be voltage drop across footer transistor which
reduces effective Vds and Ids as well
￭ Footer/header should be optimized to balance performance and leakage loss.
￭ Optimization is more complicated in coarse-grain approach.
Fig. Source bias and reduced power supply for coarse-grain
F. Dynamic Body-Biasing
Threshold voltage Vt:
VT  VTO   ( | 2F  VSB |  | 2F |)
￭ Vt can be modulated by applying different Vsb:
• Vsb<0, Vt increases, Id decreases
So, less leakage, more delay( lower performance)
• Vsb>0, Vt decreases, Id increases
So, more leakage, less delay( higher performance)
￭ Like Dynamic voltage scaling(DVS) circuit can be partitioned as
• Timing critical blocks with Vsb>0
• Other blocks with Vsb<0
￭ Transistor body effect, γ is crucial in the effectiveness of this dynamic bodybiasing approach.
G. Non-minimum Channel Length
￭ Sub-threshold current (Ioff, Ion) reduces with larger channel length( Lg)
￭ Longer channel (Lg>Lnominal ) is effective in reducing sub-threshold leakage in
trading off small performance and area. But it might increase gate and junction
leakage.
￭ In deep sub-micron process, gate and junction leakage is dominant in HVT
device leakage. So, longer channel is not useful for HVT dominant designs. Its
only useful for LVT and SVT dominant designs.
￭ This concept can be implemented
in library design level by offering
nominal and super-nominal standard
cells.
￭ Transistors in standard cells can be
swapped from nominal Lg to
longer Lg to reduce leakage.
Conclusions
￭ Standby leakage and active power have become the key issue of
continued CMOS transistor scaling.
￭ For low-power design, one needs to consider energy dissipation,
speed, area, and design–time.
￭ Good design is required in trading off performance and leakage.
￭ This paper reviewed circuit design techniques and the
corresponding implications on transistor optimization from the
leakage and active-power management perspective.
Conclusions
￭ Standby leakage and active power have become the key
issue of continued CMOS transistor scaling.
￭ For low-power design, one needs to consider energy
dissipation, speed, and area.
￭ Good design is required in trading off performance and
leakage.
￭ This paper reviewed few key circuit design techniques
and the corresponding implications on transistor
optimization from the leakage and active-power
management perspective.
References
[1] M.Chang, C.Chang,C.Chao,K.Goto,M.Leong,L.Lu,and C.Diaz, “Transistor- and CircuitDesign Optimization for Low-Power CMOS”, IEEE Transactions on Electron Devices,
January 2008.
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future of CMOS”, in IEDM Tech. Dig.,2005 pp.11-17
[3] A.Khakifirooz and D.A.Antoniadis, “Transistor performane scaling: The role of virtual
source velocity and its mobility dependence”, in IEDM Tech. Dig., 2006.pp.667-670
[4] P.Gupta,A.B,Kahang,P.Sharma,and D. Sylvester, “ Gate-length biasing for runtime leakage
control”, IEEE Trans. Comput. Aided Design Integr. Circuits Syst., vol.25,no.8,pp.14751485,Aug.2006
[5] J.Rabaey,A.Chandrakasan, and B.Nikolic, “ Digital Integrated Circuits A Design
Perspective”, 2nd ed, Prentice Hall,2003
[6] Y.Taur, “CMOS design near the limit scaling”, IBM Journal of Research and Dev.,Vol. 46,
number 2/3,2002