Transcript Document

CS 3510 - Chapter 3 (3A and 10.2.2) –
Part 4 of 5
Dr. Clincy
Professor of CS
Dr. Clincy
Lecture
Slide 1
Half Adder Combinational Circuits
• Combinational logic circuits
give us many useful devices.
• One of the simplest is the
half adder, which finds the
sum of two bits.
• We can gain some insight as
to the construction of a half
adder by looking at its truth
table, shown at the right.
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Lecture
2
Full Adder Combinational Circuits
• We can change our half
adder into to a full adder
by including gates for
processing the carry bit.
• The truth table for a full
adder is shown at the
right.
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Lecture
3
Adders - Combinational
Circuits
• Just as we combined half adders to make a full
adder, full adders can be connected in series.
• The carry bit “ripples” from one adder to the next;
hence, this configuration is called a ripple-carry
adder.
Today’s systems employ more efficient adders.
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Lecture
4
Decoder - Combinational Circuits
•
•
Among other things, they are useful in selecting a memory location
according to a binary value placed on the address lines of a memory bus.
This is what a 2-to-4 decoder looks like on the inside.
If x = 0 and y = 1,
which output line
is enabled?
Output - Decoded
message
Input - Encoded
message
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Lecture
5
Decoder – another example
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Lecture
6
Multiplexer - Combinational Circuits
• A multiplexer does just the opposite of a decoder.
• It selects a single output from several inputs.
• This is what a 4-to-1 multiplexer looks like on the inside.
Depending
the “select
input”
combination,
1 of 4 data
inputs is
chosen for
output
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Lecture
If S0 = 1 and S1 = 0,
which input is
transferred to the
7
output?
Figure A.39. Multiplexer implementation of a logic function.
Multiplexer - Combinational Circuits
Can also use multiplexers to
implement logic functions
Given this truth table, group X1,X2
being 00, 01, 10 and 11 – notice
what happens with X3
• 3-input truth table can be done
with a 4-input mux
• 4-input truth table can be done
with a 8-input mux
• 5-input truth table can be done
with a 16-input mux
• Etc..
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Also explain how the Mux is used to implement
data comm’s FDM and TDM
Lecture
8
10.2.2 - Programmable Logic Devices (PLD)
All possible
combinations
of inputs
ANDed
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•••
All possible
combinations
of ANDed
inputs ORed
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Re-explain Sums of Products and relationship to PLDs
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Lecture
9
10.2.2 - Programmable Logic Array (PLA)
Ability to program a PLD, is called a PLA
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Lecture
10
10.2.2 - Programmable Array Logic (PAL)
For a PLA, both the AND
array and OR array are
programmable
For a PAL, the AND array is
programmable and the OR
array is fixed
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Lecture
11
I/O bl
PAL-lik e
block
O block
PAL-lik e
block
Figure A.45. Structure of a comple
x programmable logicvice
de (CPLD).
10.2.2 - Complex Programmable Logic Devices
(CPLDs)
CPLDs are comprised of 2 or
more PALs
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Lecture
12
I/O block
Logic block
Interconnection switch
10.2.2 - Field Programmable Gate Arrays
(FPGAs)
Figure A.46. A conceptual block diagram of an FPGA.
PAL chips are somewhat
limited in size due to the fact
they have output pins for each
sum-of-product circuit
FPGA overcome this size
limitation by using a general
interconnection.
General interconnection
PAL
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Lecture
13
CS 3510 - Chapter 3 (3A and 10.2.2) –
Part 5 of 5
Dr. Clincy
Professor of CS
• Exam #4 next week (Thursday) covering chapter
3 (section 3A and 10.2.2)
• The topic I will cover today, Sequential Circuits,
is not covered so well in the book. You can use
these slides for the next exam
Dr. Clincy
Lecture
Slide 14
NOTE
Your book doesn’t do a good job in
showing you how to derive or design
sequential circuits (using state and state
assignment tables) – the lecture will do
so – please pay close attention to the
lecture in understanding how to derive
sequential circuits
Dr. Clincy
Lecture
Slide 15
Sequential Circuits Vs Combinational Circuits
New Input
Current
State or
Output
Current State or output
of the device is
affected by the
previous states
Flip Flops
Previous
State or
Output
Circuit
Sequential Logic
Previous
State or
Output
New Input
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Circuit
Combinatorial or Combinational Logic
Current
State or
Output
Current State or output
of the device is only
affected by the current
inputs
Lecture
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Clock - Sequential Circuits
• State changes are controlled by clocks (clock ticks).
• Circuits can change state on the rising edge, falling
edge, or when the clock pulse reaches its highest
voltage – edge triggered.
• Level-triggered circuits change state when the clock
voltage reaches its highest or lowest level.
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Lecture
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Current
State or
Output
S and R stand for set and reset respectively
constructed from a pair of cross-coupled
NOR gates
the stored bit is present on the output
marked Qa
If S and R inputs are both low, maintains
the Qa and Qb in constant state,
If S (Set) is pulsed high while R is held
low, then the Qa output is forced high,and
stays high even after S returns low;
if R (Reset) is pulsed high while S is held
Dr. Clincy
low, then
the Qa output is forced low, and
stays low even after R returns low.
New Input
•
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•
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Notice how the output feeds
the input
Flip Flops
Previous
State or
Output
Circuit
Flip Flops - Sequential Circuits
Previous
State or
Output
Lecture
Think of: Given R=0 and Qa=0,
what can this be ?
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Gated SR Latch or Flip Flop
• The time at which the latch
is SET or RESET is
controlled by a CLOCK
input
• Called Gated SR Latch
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Lecture
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