Transcript DDR Evolution and Memory Market Trends

Introduction to
DDR SDRAM
Bill Gervasi
Technology Analyst
[email protected]
1
Topics to Cover
•
•
•
•
The SDRAM Roadmap
Transitioning from SDR to DDR
DDR-I 400 Overview
Market overview
2
SDRAM Evolution
5400MB/s
Mainstream
Memories
4300MB/s
3200MB/s
2700MB/s
“DDR II”
2100MB/s
3200MB/s
1600MB/s
1100MB/s
“SDR”
“DDR I”
Simple,
incremental
steps
3
Key to System Evolution
• Never over-design!
• Implement just enough new features to achieve
incremental improvements
• Use low cost high volume infrastructure
– Processes
– Packages
– Printed circuit boards
4
From SDR to DDR
Prefetch
2
Differential
Clocks
Signaling
& Power
Write
Latency
Data
Strobe
5
Prefetch
• Today’s SDRAM architectures assume an inexpensive DRAM
core timing
• DDR I (DDR200, DDR266, and DDR333) prefetches 2 data bits:
increase performance without increasing core timing costs
• DDR II (DDR400, DDR533, DDR667) prefetches 4 bits
internally, but keeps DDR double pumped I/O
• DDR-I 400 is a prefetch-2 architecture
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Prefetch Depth
CK
data
SDR: Prefetch 1
READ
Core access
time
DDR-I: Prefetch 2
DDR-II: Prefetch 4
Costs $$$
Column cycle
time
Costs $$$
Essentially free
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Prefetch Impact on Cost
SDRAM
Family
Prefetch
SDR
1
100
10 ns
1
133
7.5 ns
2
200
10 ns
2
2
266
333
7.5 ns
6 ns
2
4
400
400
5 ns
10 ns
4
533
7.5 ns
DDR-I
DDR-II
Data
Rate
Cycle
Time
High Yield =
Affordable
Starts to get REAL
EXPENSIVE!
Comparable to
DDR266 in cost
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DDR Data Timing
• Data valid on
rising & falling
edges… “Double
Data Rate”
• Source
Synchronous;
Data Strobe
“DQS” travels
with data
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From SDR to DDR
Prefetch
2
Differential
Clocks
Signaling
& Power
Write
Latency
Data
Strobe
10
DDR Clocks
• Differential clocks on adjacent traces
• Timing is relative to crosspoint
• Helps ensure 50% duty cycle
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Single Ended Clock
VREF
CK
Normal
balanced
signal
Clock
high
time
Clock
low
time
VREF
CK
Mismatched
Rise & Fall
Error!
signal
Clock
high
time
Clock
low
time
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Differential Clock
CK
CK
Normal
balanced
signal
Clock
high
time
Clock
low
time
Clock
high
time
Clock
low
time
CK
CK
Mismatched
Rise & Fall
signal
Significantly reduced symmetry error
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From SDR to DDR
Prefetch
2
Differential
Clocks
Signaling
& Power
Write
Latency
Data
Strobe
14
DDR Signaling
• SSTL_2 low voltage swing inputs
– 2.5V I/O with 1.25V reference voltage
– Low voltage swing with termination
– Rail to rail if unterminated
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Power = CV2f%#
Factors:
• Capacitance (C)
• Voltage (V)
• Frequency (f)
• Duty cycle (%)
• Power states
(# circuits in use)
Keys to low
power design:
Reduce C and V
Match f to demand
Minimize duty cycle
Utilize power states
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Power: SDR  DDR-I DDR-II
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DDR533
@ 1.8V
10
8
6
4
2
PC-133
@ 3.3V
DDR266
@ 2.5V
0
Throughput per Second per Unit Power
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From SDR to DDR
Prefetch
2
Differential
Clocks
Signaling
& Power
Write
Latency
Data
Strobe
18
Emphasis on “Matched”
DDR SDRAM
CONTROLLER
DQ/DQS
VREF
VREF
DM
VREF
VREF
Disable
• DM/DQS loading identical to DQ
• Route as independent 8bit buses
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64 = 8 x 8
• 64bit bus is 8 sync’ed 8bit buses
• Allows external “copper” flexibility
• 8 buses resync upon entry to FIFO
Copper
from
controller
to SDRAMs
x16 DDR
SDRAM
8 DQ
1 DM
1 DQS
x16 DDR
SDRAM
x16 DDR
SDRAM
x16 DDR
SDRAM
8 DQ
1 DM
1 DQS
Inside
8bit Buffer
Controller
Sync to
Controller
clock
8 DQ
1 DM
1 DQS
8bit Buffer
64bit Memory Controller Internal FIFO
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From SDR to DDR
Prefetch
2
Differential
Clocks
Signaling
& Power
Write
Latency
Data
Strobe
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Write Latency
• SDR had to keep inputs powered all the time
• Adding Write Latency to DDR allowed inputs to be
powered off between commands
• Flexible timing differences on data and address paths
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DDR-I vs DDR-II @ 400
3200MB/s
“DDR II”
2700MB/s
“DDR I”
3200MB/s
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DDR-I 400 Summary
• DDR-I is hard to design to 400 MHz data rate
– Lower yields
• No JEDEC standard
• Prefetch-2, 2.5V signals, TSOP packages, write latency 1
– DDR-II makes it a lot easier
•
•
•
•
JEDEC standards & focus
Prefetch-4, 1.8V signals, differential strobe
On-die termination, BGA packages, write latency > 1
Same plane referencing
• Few suppliers supporting DDR-I 400 market
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DDR-I 400 Conclusion
• The JEDEC roadmap represents the industry
focus for mainstream products
– DDR-I tops out at 333 MHz data rate
– DDR-II starts at 400 MHz data rate
• This DOES NOT mean that DDR-I at 400
MHz data rate will not ship in volume
• It DOES mean that there will be price
premiums for this speed bin
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Market Outlook
• DDR-I
– DDR333 is the mainstream product for 2003
– DDR-I 400 will be the premium market
• DDR-II
– DDR-II designs under way now
– DDR-II 400 & 533 will sample in 2003
– DDR-II ramp begins in 2004
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Summary
• DDR has many improvements over SDR
– Prefetch, differential clock, low voltage, data
strobe, write latency
• DDR-I 400 likely to stay a profitable niche
• DDR-II volume products for 400 & 533 ramp
in 2004
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Thank You
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