Transcript Document

Designing CMOS Circuits for the Next Generation of
Solid-State Memory Technology
R. Jacob Baker, Ph.D., P.E.
Professor and Chairperson
Department of Electrical and Computer Engineering
Boise State University
1910 University Dr., ET 201
Boise, ID 83725
[email protected]
Abstract – The current solid-state nonvolatile memory market is dominated by MOS
technology that uses floating gate MOSFETs (Flash memory). Flash technology is mature
but faces some difficult issues with regard to scaling and thus increased density. A class of
memory cells currently under development is based on magnetic- and glass-based
materials that display resistive characteristics. The variation of the resistance with some
applied electrical stimulus must be sensed and interfaced with standard CMOS electronics.
This talk will provide: an overview of resistive memory cell operation, design concerns
when sensing to keep from affecting the contents of the cell while maximizing the signal
available for sensing, and how precision components can be eliminated with the use of
some simple signal processing techniques. The talk will conclude with a design example
showing how the techniques can be applied to solve the sensing problem in a magnetic
RAM.
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Talk Outline
 The memory market
 Overview of various (potential) memory cells
 Electrical considerations when programming and erasing
 Techniques for robust CMOS circuit design
 Conclusions and a design example
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Historical PC Market Growth
60,000,000
35%
Units in Millions
50,000,000
25%
20%
40,000,000
15%
30,000,000
10%
5%
20,000,000
0%
- 5%
10,000,000
- 10%
Grand Total
3Q05E
1Q05
3Q04
1Q04
3Q03
1Q03
3Q02
1Q02
3Q01
1Q01
3Q00
1Q00
3Q99
1Q99
3Q98
1Q98
3Q97
1Q97
3Q96
1Q96
3Q95
- 15%
1Q95
0
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Year ov er Year Growth
30%
Grand Total
3
Price per Bit
1000.0000
100,000.00
100.0000
Pric e per B it (Millic ents )
Pric e per B it (Milic ents )
10,000.00
1975
1979
1977
1974
1980
1979
1976
1981
1984
19811978
1983
19821980
1983
10.0000
1,000.00
1988
1985 1987
1982
1989
1985
1989
1984
19901993
1986 1987
1995
1991
1993
H istoric al
1995
1991
1986 1988
1994
pric e-per-bit decline has
1996
1992
1990
averaged 35.5%
1994
1997
1992
1997
(1978 - 2002)
2000
1998 1996
1999
1999
2003
1998
2001
2001
2004F 2003
2005F
2000
2002
2005
2006F
2007F
2002 2008F
1.0000
100.00
0.1000
10.00
0.0100
1.00
0.0010
0.10
2004
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)
1,000,000
10,000
Cumulativ e Bit V olume (10
100,000,000
Source: Gartner, 05/05
100
1
0.01
0.0001
4
Flash Communications and Networking Market (2005)
Cellular Phones
Cable Modems
Units - 740M
Flash – 87MB
Units – 15.7M
Flash – 2MB
DSL Modems
Units – 55M
DRAM – 8MB
Flash –2MB
Cellular Base Stations
Units - 0.35M
Flash – 5112MB
 What about Flash in personal storage devices?
 Music players (the ubiquitous iPod)
 Hardisk replacement using Flash?
 What other markets are there for nonvolatile memory (NVM)?
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NAND Flash Revenue History and Forecast
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Glass-Based Memory Cells (first flavor)
Programmable Resistance RAM (PRRAM)
Metal
Erased cell
Silver
Metal
Think of as
Glass
1 MEG
Silver
Dielectric
Vcell
Metal
Glass
Metal
Metal
Programmed cell
Silver
Think of as
Glass
10k
Metal
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SEM of PRRAM bit
Metal
Ag
Glass (doped)
Courtesy of Dr. Kris Campbell, Boise State University Department of Electrical and Computer Engineering
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Glass-Based Memory Cells (second flavor)
Source: Ovonyx - http://www.ovonyx.com/technology.pdf
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Chalcogenide Materials
 Used for compact disks (CDs) and digital versatile disks (DVDs)
 Use a laser diode to heat the material for programming
 Use the laser diode for reading the data as well - looks for a reflection or
the absence of a reflection
 One goal of this work is to remove the laser diode and use CMOS
electronics for programming and erasing.
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Programming the cell (either flavor)
Current through cell.
Going from Erased to Programmed
One over the slope is the
device’s resistance.
Programmed
Erased
Voltage across cell.
0.25 V
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| Vcell |
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Programming the cell (cont’d)
Current through cell.
Going from Programmed to Erased
Programmed
Erased
Voltage across cell.
0.25 V
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Vcell
12
Key Points when Sensing (PRRAM)
 Must keep voltage across the cell to less than +/- 0.25 V
 More desirable - minimize the voltage across the cell
 Increases retention time
 Increases lifetime
 Makes sensing more challenging
 Makes process shifts in the actual switching voltage irrelevant
 Minimizes power dissipation
 Must use an access device
 Eliminates the possibility of 3D integration
 Makes sensing much less challenging than sensing in MRAM
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Magnetic Materials-Based Cells
Read current
Free ferromagnetic (FM)
layer
Tunnel barrier
Pinned ferromagnetic (FM)
layer
Tunnel magnetoresistive effects
States
or
parallel
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antiparallel
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MRAM Cell Operation
 MRAM utilizes magnetic storage elements (rather than capacitors as in
DRAM) to form arrays of individually accessible bits.
 The main concept behind reading the data is based on the
Magnetoresistive (MR) effect.
 MR occurs when the resistance of the memory cell depends upon the
magnetic alignment of two separate magnetic layers. If the magnetic
layers are aligned, the electrons are scattered less (lower R) than if the
layers are not aligned.
 The method of writing the data is based on the generation of a magnetic
field around a wire with the flow of current in the wire.
 A current run through orthogonal conductors over or under the magnetic
element can change the orientation of the magnetic moment of the
element by 180 degrees, thereby writing a “1”, or a “0” into the cell.
 The MR ratio is given as a percentage, and is the difference in resistance
(between the two magnetic alignment states) divided by the original
resistance.
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Resistive Memory Arrays
VDD/2
VDD/2
VDD/2
VDD/2
VDD/2
VDD/2
Silver electrode
 PRRAM must use an
access device because of
the common VDD/2 node.
 Can’t be integrated in the
third dimension (up).
 For sensing we think of the
cell as a resistor connected
to VDD/2.
 The main parasitic of
importance is the bitline
capacitance.
Wordline 1
PRRAM cell
Wordline 2
Bitline 1
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Bitline 2
Bitline 3
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Cross Point Array Layout
Word lines
Layout of the MRAM cross point array
Mbit
Mbit
Mbit
Mbit
Mbit
Mbit
Mbit
Mbit
Mbit
Digit, bit, or column lines
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Cross Point Array (cont’d)
 MRAM, theoretically,
doesn’t require an access
device.
 Cell size can approach a
size of 4F2
 If the cells are integrated
in the third dimension the
cell size is further
reduced.
 Integrating 4 planes of
MRAM result in a cell
size of F2
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Mbit
Mbit
Mbit
Mbit
Cell area = 4 x FW x FC
Column (aka bit or digit) line
pitch = 2 x FC
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3 Conductor MRAM Cell
Cross sectional view of the MRAM array.
Mag stack
Sense line
Word line
Mag stack
Sense line
Mag stack
Sense line
Column line
Column line
Column line
 In a practical MRAM cell a second write conductor can be
added to avoid breakdown.
 What we’re not discussing (and these are big): half-select
problems (how to isolate the magnetic fields to a localized
region), laying down consistently thin (say 10 Angstroms)
magnetic materials, and getting large, and repeatable, TMRs.
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Circuit View of the Cross Point Array
Varray
Bitline 1
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Bitline 2
Bitline 3
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Simplified View
Varray
R
Bitline
R/(N-1)
Sneak resistance
If R is nominally 1 MEG and N is 256 (= number of
wordlines) then the sneak resistance is roughly 40k.
800k for a 1
1 MEG for a 0
0.5 V
Bitline
40k
Bitline voltage for a 0 is 0.019 V
Bitline voltage for a 1 is 0.024 V
Difference is only 5 mV!!!
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Sensing I – Traditional Circuit Techniques
 Traditional circuit
techniques require
precision components
when sensing such
small voltages.
 The cartoon illustrates
the basic idea. One guy
is trying to precisely set
the rate of flow out of
the bucket. The other
guy is timing to see
how long it will take for
the bucket to empty.
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The Equipotential Scheme
 The op-amp is trying
to precisely set the
flow of current out of
the capacitor.
 If everything is
perfect there will be
zero current through
the 40k sneak
resistance.
 A comparator and
counter determine
how long it takes to
discharge the
capacitor.
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VDD
Close to fill the bucket
Ideally held at 0.5 V by op-amp
Bucket
800k for a 1
1 MEG for a 0
0.5 V
40k
0.5 V
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Equipotential Problems
 With only 1 mV of offset
the sneak path current is
20% of the signal current.
 What happens if the offset
varies, or more practically,
the op-amp has finite gain?
 The desired signal will get
lost as a result of the opamp’s imperfections.
 Remembering our cartoon,
we can’t precisely adjust the
water flow out of the
bucket.
Baker
If there is a 1 mV offset
this node is 0.501 V
0.5
0.5

 125 nA
800 k 1 MEG
0.5 V
1 mV
 25 nA
40 k 
40k
0.5 V
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Some Other Practical Problems
 Integration time (the time it takes to empty the bucket)
 Very dependent on the value of the resistor
 Changes with imperfections in the op-amp (offset, noise, gain)
 A more subtle problem is circuit noise
 The DC current is integrated (empties the bucket)
 The thermal noise is integrated (resulting in a power spectral density of
1/f2)
 The flicker noise is integrated resulting a PSD of 1/f3
 The problem is that increasing the size of the bucket so we can
integrate longer (using a larger capacitor) will not result in a better
estimate for the current. (The signal-to-noise ratio won’t increase with
longer integration times.)
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Sensing II – Using Signal Processing
 Using some simple
signal processing (here
averaging) results in a
robust sensing scheme.
 The cartoon illustrates
the basic idea. One guy
is adding water to the
bucket in order to hold
the water level at a
constant value. The
other guy is counting
the number of added
cups of water, over a
given time.
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Bucket
Cup
Signal we are trying to measure.
Used
to fill
cup
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Qualitative Explanation
 The bucket never empties in this scheme
 The integration time is not important (we can sense indefinitely).
 The size of the cup that adds water is important.
o Using too small of a cup results in the water draining out of the
bucket. (We can’t add the water fast enough).
o Using a small cup for adding water increases the resolution.
 What happens if the guy adding water to the bucket tries to hold
the water level at a line other than the correct line (an offset)?
 As long as he attempts to hold the water level at a constant value
the actual level is unimportant (offset doesn’t matter).
 What limits the resolution of this scheme? 1) A leaky bucket, and
2) imperfectly filling the cup (or slopping water out of the cup).
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Qualitative Example
 Example: We add a cup of water, at most, every 10
seconds. Our cup size is 10 oz.
 Say that the bucket is draining at a rate of 0.3 oz per
second. We can write (assuming we want to keep,
arbitrarily, 100 oz of water in the bucket):
Baker
Time (secs)
Add cup?
Bucket Vol. (oz)
Average # cups
0 (1)
Y
100
1 (1/1)
10 (2)
N
107
0.5 (1/2)
20 (3)
N
104
0.333 (1/3)
30 (4)
N
101
0.25 (1/4)
40 (5)
Y
98
0.4 (2/5)
50 (6)
N
105
0.333 (2/6)
60 (7)
N
102
0.286 (2/7)
70 (8)
Y
99
0.375 (3/8)
80 (9)
N
106
0.333 (3/9)
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Qualitative Example (cont’d)
 Continuing we can write (noting it doesn’t matter if
our first decision was an add or not).
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Time (secs)
Add cup?
Bucket Vol. (oz)
Average # cups
80 (9)
N
106
0.333 (3/9)
90 (10)
N
103
0.300 (3/10)
100 (11)
Y
100
0.364 (4/11)
110 (12)
N
107
0.333 (4/12)
120 (13)
N
104
0.308 (4/13)
130 (14)
N
101
0.285 (4/14)
140 (15)
Y
98
0.333 (5/15)
150 (16)
N
105
0.313 (5/16)
160 (17)
N
102
0.294 (5/17)
180 (18)
Y
99
0.333 (6/18)
190 (19)
N
106
0.316 (6/19)
200 (20)
N
103
0.300 (6/20)
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Qualitative Example (cont’d)
 Note how, as we increase the number of samples,
the average bounces around 0.3.
 The more samples we take the more the average
converges on 0.3
 The signal is the product of the average and the cup
size or 0.3*10 (which is 3 oz per 10 seconds).
 Note that if we make a wrong decision it doesn’t
really matter.
 If we add a cup when we shouldn’t have it really
doesn’t matter! (Comparator gain isn’t important.)
 A counter is used for averaging (count the number of
times we add water to the bucket).
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Resolution and Precision
 Again, the resolution is set by the size of the cup we use to add
water to the bucket.
 Smaller cup, faster, more accurate sense.
 If the cup is too small we can’t add water fast enough.
 The precision is set by how accurately we add the water to the
bucket.
 Spilling water out of the cup reduces the sensing accuracy.
 The ultimate resolution is determined by how leaky the bucket
is (keeping in mind that in a circuit an integrator is used for the
bucket.)
 Note that the longer we sense the better the sense. (We don’t
have to worry about the bucket emptying.)
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Self-Referencing
 So we have a counter code. How do we determine if we
read a 1 or a 0?
 Consider the following: Say a 1 corresponds to a counter
code of 222 and a 0 corresponds to 220.
 Reading a 1
 Perform two reads on the cell. The counters contents are 444.
 Write a known 1 into the cell. Make the counter count down
instead of up during a sense. The counters contents are now
222.
 Write a known 0 into the cell. Again, make the counter count
down. The counters contents are 2. Since the number is
positive the cell must be a 1. (Rewrite a 1 to the cell).
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Self-Referencing (cont’d)
 Reading a 0 (again a 1 corresponds to 222 and a 0 to 220)
 Perform two reads on the cell. The counters contents are 440.
 Write a known 1 into the cell. Make the counter count down
instead of up. The counters contents are now 218.
 Write a known 0 into the cell. Again, make the counter count
down. The counters contents are 2. Since the number is negative
the cell must be a 0. (Rewrite a 0 to the cell).
 Note that we can reduce the sensing time by performing one
read and then multiplying the result by 2.
 This self-referencing technique eliminates process, voltage, and
temperature concerns. Even if the bit resistance has a long term
variation as long as the short term variation is small the sensing
works as expected.
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Design Example1 – Sensing in an MRAM
1Leslie,
M.B., and Baker, R.J., (2006) "Noise-Shaping Sense Amplifier for MRAM Cross-Point Arrays," IEEE Journal of Solid State
Circuits, Vol. 41, No. 3, pp. 699-704.
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Circuit Block Diagram
 Sensing architecture using noise-shaping with MTJ.
 One sense-amplifier per bit line (column line)
 Note that there is nothing under the memory array (so we can use
the real estate for our sensing circuit
 Must be low noise and very tolerant to ground and VDD noise
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Sensing Circuit Block Diagram
 For microvolt sensitivity we must use very large forward gain
 The additive noise source, E, models the quantization noise from the
comparator.
E
vIN  g
m1
S
v1
C1
 gm2
S
v2
S
vOUT
Tt
C2
gm3
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Sensing Circuit Schematic
VDD
VDD
VDD
VDD
VDD
vIN
v1
C1
v2
Comparator
vOUT
Out to counter
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C2
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Sensing Experimental Results
 Sense-amp behaves like a voltage meter.
 Used probe station to gather results. (DC voltage ran through wires to
a 1000:1 resistive divider on the wafer at the input of the sense amp!)
 With 1 MRAM plane sense signal is 2 mV (4 planes sense signal is
500 uV)
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Sense time vs SNR
 How does the sensing time affect SNR?
Sense margin figure of merit
45
40
delta avg / avg(sigm as)
35
30
25
20
15
10
5
0
50
100
200
400
1000
# counts
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On Going Research
 Working towards making the glass-based memories
manufacturable
 How do we use averaging to both program and sense?
 Exploring, with the materials engineers, the best approach
for success
 Looking at multi-level cell design (variable resistances)
 Applying the techniques to multi-level cell programming
in Flash memory
 An example of a mature technology that may benefit from
clever circuit design using signal processing (the current
method of program then verify and repeat is slow and
imprecise)
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Questions?
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