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A 12-mW ADC Delta–Sigma Modulator With
80 dB of Dynamic Range Integrated in a
Single-Chip Bluetooth Transceiver
IEEE JSSC, VOL. 37, NO. 3, MARCH 2002
Jorge Grilo, Member, IEEE, Ian Galton, Member, IEEE, Kevin Wang, Member, IEEE,
and Raymond G. Montemayor, Associate Member, IEEE
Wei-Chih
2009/04/02
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Outline
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Abstract
Introduction
Bluetooth receiver architecture
Delta–sigma modulator topology
Circuit design
Experimental results
Conclusions
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Abstract

SC multi-bit ADC DSM for baseband demodulation integrated
in a single-chip Bluetooth radio-modem transceiver.
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SNDR=77dB,DR=80dB ,fs=32MHZ at BW=500KHZ.
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The 1-mm2 circuit is implemented in a 0.35-μm BiCMOS SOI
process and consumes 4.4 mA of current from a 2.7-V supply.
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Introduction
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Direct down-conversion receivers are promising
 Off-chip filters. (Minimize)
 Much of the signal processing to be performed efficiently in
the digital domain.
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Combination of high dynamic range and low power dissipation
 Low-order DSM with multi-bit quantization and a BiCMOS
process.
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Multi-bit quantization made problem
 Mismatch-shaping DACs modified to reduce processing
latency.
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Bluetooth receiver architecture
C
A
B
A:Low noise amplification.
B:Quadrature down-conversion.
C:Anti-aliasing filter.
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Digital domain
 Channel filtering, Demodulation, and clock and data
recovery.
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Delta–sigma modulator topology (cont.)
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Higher order single-loop architecture with one-bit quantization
or a MASH architecture could have been used instead.
 One-bit=lower input no-overload range.
 Less aggressive quantization noise shaping=higher order.
 N order=requiring N+1 opamps. (Power consumption)
 Analog and digital in the presence mismatching. (MASH)
 Inherent loss in DR due to internal signal scaling.
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Delta–sigma modulator topology
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In contrast the multi-bit second-order architecture
 Only two opamps. (Low current consumption)
 Its no-overload range is nearly equal to its reference voltage.
 Allows for smaller input sampling capacitors.
 Mismatch-shaping DACs the current consumed by this
logic is small compared.
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Circuit design (cont.)
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Switched-capacitor top-level design
Scaling coefficients
 First:confine the high-gain most linear region of the
amplifiers.
 Second:comply with the input common-mode
requirements of the comparators in the internal flash ADC.
 Third:loading conditions of clock phases, choice of the
input capacitor size. (Optimum)
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Circuit design (cont.)
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Operational amplifier
 Two-stage miller-compensated configuration.
 Bipolar devices in the second stage results in ease of phase
compensation at very modest current levels. (& CMOS)
 BW=350MHZ,Gain=80dB,PM=80°,Vcm=1.35 V
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Circuit design (cont.)
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Comparator Used in the Flash ADC
 The use of bipolar devices at the input stage resulted in a
design with low input-referred offset at low current levels.
 The estimated deviation of the input-referred offset is 4 mV.
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Circuit design (cont.)
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The Feedback Path
Mismatch noise shaping digital encoder
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Circuit design (cont.)
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swapper cell
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Circuit design (cont.)
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He digital encoder is designed to suppress the power of the
DAC noise in the frequency band below 500 KHZ.
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Circuit design
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Simulated Results
Simulation output spectrum
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Measured output spectrum
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Experimental results (cont.)
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Signal freq=31.25KHZ
SNDR=77dB
DR=80dB
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Experimental results
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Conclusions

DSM ADC for direct-conversion Bluetooth radio-modem
transceive.
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Mismatch-shaping DAC logic for minimize latency.
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Bipolar (npn) transistors in the opamps and comparators also
resulted in current savings.
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