Transcript Solid State Physics II

Final Exam (Review Next Class,
Allowed One Sheet of Notes)
• Currently scheduled at 7pm Tuesday (blah)
• If we can all agree on the same time MonWed, then we can move it
Possibilities
Monday
10 am
1 pm
3 pm
Tuesday
10 am
1 pm
Wednesday
10 am
1 pm
3 pm
Normal exam times start at 8am, 11am, 3pm, 7pm
Last time: Donor Impurities Contribute Electrons
The free electrons in n type silicon support the flow of current.
Acceptors
-ve
ion
+e
• Again use example: silicon (Si)
– Substitute one Group III atom (e.g. Al or In) with
a Si (Group IV) atom
– Si atoms have 4 electrons for covalent bonding
– When a Group III atom replaces a Si atom, it
cannot complete a tetravalent bond scheme
– A hole is formed.
– If the hole leaves the impurity, the core would be
negatively charged, so the hole created is then
attracted to the negative core
– At T = 0 K this hole “stays” with atom – localized
hole
Acceptors
• At T > 0 K, electron from the
neighboring Si atom can jump
into this hole – the hole starts to
migrate, contributing to the
current
• We can say that this impurity
atom accepted an electron, so we
call them Acceptors
• Acceptors accept electrons, or
they “donate holes”
• Such semiconductors are called ptype semiconductors since they
contribute positive charge carriers
This crystal has been doped with a trivalent impurity.
The holes in p type silicon contribute to the current.
Note that the hole current direction is opposite to electron current
so the electrical current is in the same direction
Acceptor: Energy Levels
– Such impurities create “shallow” levels - levels
that are very close to the valence band
– Energy to ionize the atom is still small
– They are similar to “negative” hydrogen atoms
– Such impurities are called hydrogenic acceptors
Examples
Since holes are generally
heavier than electrons, the
acceptor levels are deeper
(larger) than donor levels
Why the range?
EDonors
me* 1
~ 13.6
eV
2
m0 
The valence band has a
complex structure and this
formula is too simplistic to
give accurate values for
acceptor energy levels
Acceptor energy levels
are bigger. Why?
–
–
–
–
–
Ge: 10 meV
Si: 45 – 160 meV
GaAs: 25 – 30 meV
ZnSe: 80 – 114 meV
GaN: 200 – 400 meV
Acceptor and donor
impurity levels are often
called ionization energies
or activation energies
Impurity Bands
Have considered the impurities as isolated atoms. Reasonable as
doping level normally ~ one donor per 106 semiconductor atoms.
At very high donor concentrations, one has substantial overlap
between the donor or acceptor wavefunctions.
f(r)
aB
+
b
+
Above a critical doping level one has an impurity energy band with a
finite conductivity.
Electron density at which this “metal insulator transition” occurs?
aB ~ 50 Å & lattice constant, a ~ 2.5 Å.
Need b ~ aB = 20a . i.e. one donor per 203 = 8000 semiconductor atoms
8
Mott Transition
• Impurities get close enough to form their own bands
when wavefunctions overlap
• Causes the material to become a metal
• Also happens for high density Excitons  forms plasma
Carrier Concentrations in
Extrinsic Semiconductors
• The carrier densities in extrinsic semiconductors can
be very high
• Depends on doping levels and ionization energy of
the dopants
• Often both types of impurities are present
– If the total concentration of donors (ND) is larger
than the total concentration of acceptors (NA)
have an n-type semiconductor
– In the opposite case have a p-type semiconductor
How can we measure whether
our material is more n or p
type?
In a current carrying wire when in a perpendicular magnetic field,
the current should be drawn to one side of the wire. As a result,
the resistance will increase and a transverse voltage develops.
e- v
e+ v
Current from the
applied E-field
Lorentz force from the magnetic field
on a moving electron or hole
Top view
e- leaves + & – charge on
the back & front surfaces–
Hall Voltage
Top view—electrons The sign is reversed for holes
drift from back to front
Standard Hall Effect Experiment
Charge Neutrality Equation

D
pv  pa  N  nc  nd  N
pv
nc

A
For an intrinsic semiconductor, nc = pv
Simplify: Consider n-type
semiconductor with small NA~0

D
pv  pa  N  nc  nd  N

A
Conduction
Band

D
Ec = Eg
ED
pv  N  nc  nd
What is nd at T=0?
At T>>0, nd ~ 0

D
pv  N  nc
Valence
Band
Ev = 0
Compensated semiconductor

D
pv  pa  N  nc  nd  N

A
Conduction
Band
ND donors per m3 and NA acceptors per m3
Ec = Eg
ED
For ND > NA have an n-type S.C.
with n ~ ND - NA for T ~ 300K
For NA > ND have an p-type S.C.
(homework)
NA electrons fall into
acceptor states
EA
Valence
Band
Ev = 0
Don’t overthink final homework. Just wants you to explain where carriers go in
terms of formula. Start by discussing where the levels are.
All solid-state electronic
and opto-electronic
devices are based on
doped semiconductors.
In many devices the doping and hence
the carrier concentrations vary.
In the following section we will consider the p-n junction
which is an important part of many semiconductor
devices and which illustrated a number of key effects
Bringing Two Semiconductors
Together
p-type / n-type semiconductor
considerations
We will consider the p-n
interface to be abrupt -- a good
approximation.
Before we let charges move:
n-type ND donor atoms per m3
p-type NA acceptor atoms per m3
Consider temperatures ~300K
Almost all donor and acceptor
atoms are ionized.
impurity atoms m-3
ND
NA
p-type
n-type
x=0
xa
ND (x) = ND (x>0) = 0 (x<0)
NA (x) = NA (x<0)
(x>0) = 0 (x>0)
(x<0)
p-type semiconductor
What
happens?
n-type semiconductor
Electrons
EC
m
EC
m
EV
EV
Holes
Consider bringing into contact p-type and n-type semiconductors.
n-type semiconductor: Chemical potential, m below bottom of
conduction band
p-type semiconductor: Chemical potential, m above top of valence
band.
Electrons diffuse from n-type into p-type filling empty valence states.
Do they fill all of them?
Note: n and p sides are reversed in this diagram
compared to others..
Originally lots of
free carriers of
opposite types in
each material.
Then joined.
Each e- that departs
from the n side leaves
behind a positive ion.
Electrons enter the
P side and create neg.
ion.
The immediate
vincinity of the junction
is depleted of free
carriers.
Band Bending
n-type
p-type
Electrons
EC
p-type semiconductor
EC
m
EC
Before Contact
m
EV
Electrons
EC
m
EV
Holes
n-type semiconductor
ef0
EV
EV
Holes
p-type semiconductor
n-type semiconductor
A large electric field is produced close to the interface. Which way?
Electron energy levels in the p-type rise with respect to the n-type material.
Dynamic equilibrium results with the chemical
potential (Fermi level) constant throughout the device.
Note: Absence of electrons and hole close to interface Compare to metals
-- This is called the depletion region.
Depletion region
Depletion region
Assume the electric field in the
region of the junction removes all
the free carriers creating a
depletion region for –dp<x < dn.
n-type
p-type
n,p
Electron and
Hole Density
r
The ionized impurities are fixed in
the lattice. So charge density is
r  +eND per m3 for 0 <x <dn
r  –eNA per m-3 for -dp < x < 0.
Net charge
density
E
-dp
0
Depletion region
dn
xa
The total charge in the depletion region must be zero
as the number of electrons removed from the right
equals the number of holes removed from the left
i.e.
NDdn = NAdp.
Electric field in pn junction
We can calculate the electrostatic potential, f(x) from the Poisson’s
equation. Group: Find the electric field for all x.
 2V ( x)
  r ( x) /  0 r
2
x
Charge density: r(x) = eND for 0 < x < dn r(x) = -eNA for –dp < x < 0
Boundary condition: E = 0 for x > dn and x < –dp
Depletion region
So integration gives
V  N Ae
E 
( x  d p ) for  d p  x  0
x  0 r
V  N D e
E 
( x  d n ) for 0  x  d n
x  0 r
Net charge
density
p-type
r
n-type
E
Electric Field
(negative)
0
xa
Electrostatic potential, f(x)
Integration of E gives the potential V(x).
Since V  0 for x < –dp and V   V0 for x < dn.
eN A
V ( x) 
( x  d p )2
2 0 r
V ( x)  0 
eND
( x  dn )2
2 0 r
V(x) is continuous at x = 0 so
for
0  x  dn
e( N D d n  N Ad p )
2
V0 
So since NDdn = NAdp
 dp  x  0
for
 2 0 r N A V0 
dn  

eN
(
N

N
)
D 
 D A
2
2 0 r
1
2
 2 0 r N D V0 
dp  

eN
(
N

N
)
D 
 A A
Resulting depletion width is ~100nm to 1mm
1
2
Electron and
Hole Density
n,p
n-type
p-type
r
Net charge
density
E
Electric Field
(negative)
Electrostatic
Potential
Energy of
Conduction
band edge
V(x)
EC
0
Depletion layer
xa
Different ways of Crossing PN
Junction
Diffusion
Diffusion
np=ni2
Drift
Drift
Majority carriers cross the pn junction via diffusion (because you have the gradient)
Minority carriers cross the pn junction via drift( because you have the E, not the gradient)
PN Junction under Reverse
Bias Reverse: Connect
the + terminal to the
n side.
Depletion region widens.
Therefore, stronger E.
E
Minority carrier to cross
the PN junction easily
through drift.
Current is composed
mostly of drift current contribut
by minority carriers.
np to the left and pn to the righ
Current from n side to p side,
Forward Bias Diode
Electric Current
Net flow of electrons
EC
p-type
m
EV
EC
m
eV
n-type
e(f0V)
Net flow of holes
p-type biased positive
EV
n-type biased negative
Depletion region shrinks due to charges from the battery.
The electric field is weaker.
Majority carrier can cross via diffusion; Greater diffusion current.
Current flows from P side to N side
Applications of p-n junctions
• Excellent diodes, which can be used for
rectification (converter of AC to DC).
• Light emitting diodes (LEDs)
and lasers: In forward bias one
has an enhanced recombination
current. For direct band gap
semiconductors, light is emitted.
• Solar cells: If photons
with hn>Eg are absorbed
in the depletion region,
get enhanced generation
current. Photon energy
can be converted to
electrical power.
Recombination Current
EC
ef0
Photons Out
EC
m
EV
ef0
EV
p-type semiconductor
n-type semiconductor
Electrons with energies greater than eΔ0 can move into the p-type
material where they recombine with holes.
A recombination current, Jrec, in the positive x-direction results
Jrec = B exp(-e Δ0/2kBT) where B is ~ constant.
For direct band gap semiconductors recombination leads to photon emission
The MOS-FET
•In the MOS device, the gate electrode, gate oxide,
and silicon substrate from a capacitor.
•High capacitance is required to produce high
transistor current.
Cgate = K0A / d
Silicon (p doped)
K = dielectric constant, 0 = permittivity of vacuum
A = area of capacitor, d = dielectric oxide thickness
Making Computers Smaller
Cgate = K0A / d
K = dielectric constant, A = area of capacitor, d = oxide thickness
Area
Speed
Area
Capacitance
Capacitance
Thickness
Replacement Oxides
• High dielectric constant
• Low leakage current
• Works well with current Si technology
Many materials have been tried but none are as
cheap and easy to manipulate as existing SiO2.
What else can we do?
• We’ve looked at metal-metal and
semiconductor-semiconductor interfaces.
• How about metal-semiconductor boundaries?
33
Metal-semiconductor (MS)
junctions
•Many of the properties of pn junctions can be
realized by forming an appropriate metalsemiconductor rectifying contact (Schottky
contact)
– Simple to fabricate
– Switching speed is much higher than that of p-n junction
diodes
•Metal-Semiconductor junctions are also used as
ohmic-contact to carry current into and out of the
semiconductor device
Ideal MS contacts
n-type
Assumptions - Ideal MS contacts
M and S are in contact on atomic scale
No oxides or charges at the interface
No intermixing at the interface
What happens when a metal and
semiconductor are brought
into contact?
When charges are brought near a metal surface,
negative (IMAGE) charges are induced in the metal.
Metal
- - - - - - + + + + + + +
Semiconductor
n-type
Once connected, as in a p-n junction, charge transfer
occurs until the Fermi levels align at Equilibrium.
What happens when a metal and
semiconductor are brought
into contact?
As in a p-n junction, a depletion region forms near the junction.
d
Metal
- - - - - - + + + + + + +
Semiconductor
n-type
• The positive charge due to uncompensated donors within d
matches the charge on the metal.
• The behavior of the junction will depend on the work
functions.
Energy band diagrams for ideal
MS contacts
Difference
(a) and (c) An instant
after contact formation
(before movement of
charges)
(b) and (d) under
equilibrium conditions
M > S
M < S
MS (n-type) contact with M > S
• Soon after the contact formation, electrons will
begin to flow from S to M near junction.
•Creates surface depletion layer, and
hence an electric field (like in pn
junction).
•Under equil., net flow of carriers will
be zero, and chem pot will be constant.
•A barrier B forms for electron flow
from M to S.
•B = M –  ... ideal MS (n-type)
contact. B is called “barrier height”.
MS (n-type) contact
with M > S
Response to applied bias for ntype semiconductor
Note: An applied positive voltage
lowers the band since energy
bands are drawn with respect to
electron energy.
MS (n-type) contact with  M < S
• No barrier for electron flow from S to M.
• So, even a small VA > 0 results in large
current.
• As drawn, small barrier exists for electron
flow from M to S, but vanishes when VA< 0
is applied to the metal. Large current flows
when VA< 0.
I
• The MS(n-type) contact when M < S
behaves like an ohmic contact.
VA
Schottky diode
Vbi 
1
 B  ( EC  EF ) FB 
q
r  qND
0
for 0  x  W
for x  W
dE
r
qND


dx
Si
Si
E(x)  
q ND
 Si
E(x  0)  
V ( x)  
q
for 0  x  W
W  x )
ND W
 Si
qN D
2
W  x )
2 si
0  x W
1/ 2
 2 Si

W  
(Vbi  VA )
 q ND

42
Additional Slides/Approaches
Energy band diagram of a
metal-n semiconductor contact
in equilibrium.
The work function of the semiconductor is less than that of the metal.
Because of the higher chemical potential, electrons rush from the
semiconductor to the metal. The voltage is lowered until further motion
of charges is no longer favorable.
•
Charge Density in a
Semiconductor
Assuming the dopants are completely ionized:
r = q (p – n + ND – NA)
Metal-Semiconductor
Contacts
There are 2 kinds of metal-semiconductor contacts:
• rectifying
“Schottky diode”
• non-rectifying
“ohmic contact”
EE130 Lecture 10,
EE130 Lecture 10,
Ideal MS Contact: M > S, ntype
Band diagram instantly
after contact formation:
Equilibrium
band diagram:
Schottky
Barrier :
Bn  M  
EE130 Lecture 10,
Ideal MS Contact: M < S, ntype
Band diagram instantly
after contact formation:
Equilibrium
band diagram:
EE130 Lecture 10,
EE130 Lecture 10,
Ideal MS Contact:
M < S, p-type
metal
p-type Si
Eo
Si
Ec
M
B
qVbi = Bp– (EF –
Ev)FB
p
W
EF
Ev
Bp =  + EG - M
Effect of Interface States on Bn
metal
M > S
n-type Si
•
Ideal MS contact:
Bn = M – 
•
Real MS contacts:
 A high density of
allowed energy
states in the band
gap at the MS
interface pins EF to
the range 0.4 eV to
0.9 eV below Ec
Eo
Si
M
qVbi = B – (Ec – EF)FB
B
Ec
EF
n
Ev
W
Schottky Barrier Heights:
Metal on Si
Metal
M (eV)
Bn (eV)
Er
3.12
0.44
Ti
4.3
0.5
Ni
4.7
0.61
W
4.6
0.67
Mo
4.6
0.68
Pt
5.6
0.73
Bp (eV)
0.68
0.61
0.51
0.45
0.42
0.39
 Bn tends to increase with increasing metal work function
Schottky Barrier Heights:
Silicide on Si
Silicide ErSi1.7 TiSi2 CoSi2 NiSi
WSi2
PtSi
M (eV) 3.78 4.18
Bn (eV) 0.3
Bn (eV) 0.8
4.6 4.65 4.7
5
0.6 0.64 0.65 0.65 0.84
0.52 0.48 0.47 0.47 0.28
Silicide-Si interfaces are more stable than metal-silicon
interfaces. After metal is deposited on Si, a thermal
annealing step is applied to form a silicide-Si contact.
The term metal-silicon contact includes silicide-Si
contacts.
The Depletion Approximation
The semiconductor is depleted of mobile carriers to a depth W
 In the depleted region (0  x  W ):
r = q (ND – NA)
Beyond the depleted region (x > W ):
r=0
EE130 Lecture 10,
Electrostatics
• Poisson’s equation:
• The solution is:
V x )   E( x)dx
E r qND
 
x
s
s
E x )  
qND
s
W  x )
Depleted Layer Width, W
 qND
W  x )2
V x ) 
2K S 0
At x = 0, V = -Vbi
2 sVbi
 W
qND
• W decreases with increasing ND
Schottky Diode (n-type Si)
metal
M > S
n-type Si
Depletion width:
Eo
Si
M
qVbi = Bn – (Ec – EF)FB
B
Ec
EF
n
Ev
W
2 sVbi
W
qND
Equilibrium (VA = 0)
-> EF continuous,
constant
 Bn = M – 
Schottky Diode (p-type Si)
metal
M < S
p-type Si
Eo
Depletion width:
Si
Ec
M
B
qVbi = Bp– (EF –
Ev)FB
p
W
EF
Ev
2 sVbi
W
qN A
Equilibrium (VA = 0)
-> EF continuous,
constant
Bp =  + EG - M
Current-Voltage Characteristic
At equilibrium, without a bias voltage Jgen + Jrec = 0
With external positive voltage V the Jgen is ~ unchanged, but Jrec becomes
 - (e0 - eV) 
J rec (V ) = B exp

kBT


 eV 
  1)
Total net current density is J  J rec (V )  J gen (0)  J gen (0)(exp
 kBT 
J
Reverse bias
negative
p
n
positive
Forward bias
positive
V
-Jgen
p
n
negative
Operation of a transistor
VSG
Gate
Insulator
Source
Channel
VSD
Drain
Substrate
Transistor turns on at high gate voltage
Transistor current saturates at high drain bias
Start with a MOS capacitor
VSG
Gate
Insulator
Source Channel
Substrate
VSD
Drain
MIS Diode (MOS capacitor) – Ideal
ECE 663
Questions
What is the MOS capacitance? QS(yS)
W
What are the local conditions during inversion?
How does the potential vary with position?
yS,cr
y(x)
How much inversion charge is generated at the surface? Qinv(x,yS)
Add in the oxide: how does the voltage divide?
yS(VG), yox(VG)
How much gate voltage do you need to invert the channel? VTH
How much inversion charge is generated by the gate? Qinv(VG)
What’s the overall C-V of the MOSFET?
QS(VG)
Ideal MIS Diode n-type, Vappl=0
Assume Flat-band
at equilibrium
qfS
EC
EF
Ei
EV
ECE 663
Ideal MIS Diode n-type, Vappl=0
fms
Eg


 fm    
 yB   0
2q


ECE 663
Ideal MIS Diode p-type, Vappl=0
ECE 663
Ideal MIS Diode p-type, Vappl=0
fms
Eg


 fm    
 yB   0
2q


ECE 663
Accumulation
Pulling in majority carriers at surface
ECE 663
But this increases the barrier
for current flow !!
n+
p
n+
ECE 663
Depletion
ECE 663
Inversion
yB
Need CB to dip below EF.
Once below by yB, minority carrier density trumps the intrinsic density.
Once below by 2yB, it trumps the major carrier density (doping) !
ECE 663
P-type semiconductor Vappl0
Convention for p-type: y positive if bands bend down
ECE 663
Ideal MIS diode – p-type
np  ni e
( Ei' EF ) / k T
 ni e
( Ei qyEF ) / k T
 np 0e
qy / k T
 np 0e
y
CB moves towards EF if y > 0  n increases
pp  pp0e qy / kT  pp0e y
VB moves away from EF if y > 0  p decreases

q
kT
ECE 663
Ideal MIS diode – p-type
At the semiconductor surface, y = ys
ns  np0ey
s
ps  pp0e y
s
ECE 663
Surface carrier concentration
ns  np0e
y s
ps  pp0e
ys
• ys < 0 - accumulation of holes
EC
EF
• ys =0 - flat band
• yB> ys >0 – depletion of holes
• ys =yB - intrinsic concentration ns=ps=ni
• ys > yB – Inversion (more electrons than holes)
ECE 663
Want to find y, E-field, Capacitance
• Solve Poisson’s equation to get E field,
dE density
potential based
on
charge
E  r / k 0  r /  s 
 1 D
dx
distribution(one dimension)
dy
E  
dx
d 2y
 2  r /  s
dx
r( x)  q(ND  NA  pp  np )
ECE 663
• Away from
 NDthe
 NA surface,
 np 0  pp 0 r = 0
pp  np  pp0e y  np0ey
• and
d 2y
q
 2   p p 0 (e y  1)  n p 0 (e y  1))
s
dx
ECE 663
Solve Poisson’s equation:
d 2y
q
 2   p p 0 (e y  1)  n p 0 (e y  1))
s
dx
E = -dy/dx
d2y/dx2 = -dE/dx
= (dE/dy).(-dy/dx)
= EdE/dy
d 2y
q
EdE/dy
 2   p p 0 (e y  1)  n p 0 (e y  1))
s
dx
ECE 663
Solve Poisson’s equation:
• Do the integral:
2
x
x
• LHS: xdx   x  dy
2
0
x
• RHS:
e
0
x
dx
x
dx,  dx
0
n p 0 y

 kT   qpp 0   y
e  y  1)

 e  y  1) 
 
pp0
 q   2 s  

2
E
2
field
• Get expression for E field (dy/dx):
ECE 663
Define:
LD 
kT s
s

2
qpp 0
pp 0q
Debye Length

n p 0   y
n p 0 y



e  y  1)
F  y,
 e  y  1) 

pp0  
pp0


Then:
1
2
E>0
Efield
np0 
2kT 


F  y,
qLD 
p p 0 
+ for y > 0 and – for y < 0
y>0
E<0
y<0
ECE 663
Use Gauss’ Law to find
surface charge per unit
area
np0 
2kT 


Qs   s ES  
F  y s ,
qLD 
p p 0 
Qs  
2kT
qLD
 y
 e  y s  1)  npp0 ey  y s  1)
p0


S
1
2
s
ECE 663
Accumulation to depletion to strong Inversion
• For negative y, first term in F
dominates – exponential
np 0e y

1 second term in F
• For small positive
y,
pp0
dominates - y
(kT/q)ln(N
np0)
B =y
A/ni) = (1/)ln(pp0/√pp0second
•y
As
gets larger,
exponential-2y
gets big
(np0/pp0) = e
B
yS > 2yB
ECE 663
Questions
 What is the MOS capacitance? QS(yS)
 What are the local conditions during inversion?
How does the potential vary with position?
yS,cr
y(x)
How much inversion charge is generated at the surface? Qinv(x,yS)
Add in the oxide: how does the voltage divide?
yS(VG), yox(VG)
How much gate voltage do you need to invert the channel? VTH
How much inversion charge is generated by the gate? Qinv(VG)
What’s the overall C-V of the MOSFET?
QS(VG)
Charges, fields, and potentials
• Charge on metal = induced surface
metal insul semiconductor
charge in semiconductor
• No charge/current in insulator (ideal)
depletion
inversion
QM  Qn  qN AW  QS
ECE 663
Charges, fields, and potentials
Electric Field
Electrostatic Potential
ECE 663
Depletion Region
Electric Field
Electrostatic Potential
n p 0 y

 kT   qpp 0   y
e  y  1)

 e  y  1) 
 
pp0
 q   2 s  

2
E
2
field
ECE 663
Depletion Region
Electric Field
Electrostatic Potential
y = ys(1-x/W)2
Wmax = 2s(2yB)/qNA
yB = (kT/q)ln(NA/ni)
ECE 663
Questions
 What is the MOS capacitance? QS(yS)
 What are the local conditions during inversion?
 How does the potential vary with position?
yS,cr
y(x)
How much inversion charge is generated at the surface? Qinv(x,yS)
Add in the oxide: how does the voltage divide?
yS(VG), yox(VG)
How much gate voltage do you need to invert the channel? VTH
How much inversion charge is generated by the gate? Qinv(VG)
What’s the overall C-V of the MOSFET?
QS(VG)
Couldn’t we just solve
this exactly?
Exact Solution
U = y
US = yS
UB = yB
dy/dx = -(2kT/qLD)F(yB,np0/pp0)
U
 dU/F(U) =  x/L
D

US
F(U) = [eUB(e-U-1+U)-e-UB (eU-1-U)]1/2
Exact Solution
r = qni[eUB(e-U-1) – e-UB(eU-1)]
US
 dU’/F(U’,U ) =  x/L
B
D

U
F(U,UB) = [eUB(e-U-1+U) + e-UB (eU-1-U)]1/2
Exact Solution
NA = 1.67 x 1015
Qinv ~ 1/(x+x0)a
x0 ~ LD . factor
Questions
 What is the MOS capacitance? QS(yS)
 What are the local conditions during inversion?
 How does the potential vary with position?
yS,cr
y(x)
 How much inversion charge is generated at the surface? Qinv(x,yS)
Add in the oxide: how does the voltage divide?
yS(VG), yox(VG)
How much gate voltage do you need to invert the channel? VTH
How much inversion charge is generated by the gate? Qinv(VG)
What’s the overall C-V of the MOSFET?
QS(VG)
Threshold Voltage for Strong Inversion
• Total voltage across MOS structure=
QS ys
voltage
across
dielectric
plus
V (strong _ inversion)  V  y 
 2y
T
i
QS (SI )  qNAWmax  qNA
S
Ci
B
2 s y s (inv )
 2 s qNA (2y B )
qNA
2 s qNA (2y B )
 VT 
 2y B
Ci
ECE 663
Notice Boundary Condition !!
oxVi/tox = sys/(W/2) Before Inversion
After inversion there is a discontinuity
in D due to surface Qinv
2 s qNA (2y B )
 VT 
 2y B
Ci
Vox (at threshold) = s(2yB)/(Wmax/2)Ci
=
ECE 663
Local Potential vs Gate voltage
VG = Vfb + ys + (stox/ox)√(2kTNA/0s)[ys + eys-2yB)]1/2
yox
ys
Initially, all voltage drops across channel (blue curve). Above threshold,
channel potential stays pinned to 2yB, varying only logarithmically, so that
most of the gate voltage drops across the oxide (red curve).
Look at Effective charge width
~Wdm/2
~tinv
Initially, a fast increasing channel potential drops across
increasing depletion width
Eventually, a constant potential drops across a decreasing
inversion layer width, so field keeps increasing and thus
matches increasing field in oxide
Questions
 What is the MOS capacitance? QS(yS)
 What are the local conditions during inversion?
 How does the potential vary with position?
yS,cr
y(x)
 How much inversion charge is generated at the surface? Qinv(x,yS)
 Add in the oxide: how does the voltage divide?
yS(VG), yox(VG)
 How much gate voltage do you need to invert the channel? VTH
How much inversion charge is generated by the gate? Qinv(VG)
What’s the overall C-V of the MOSFET?
QS(VG)
Charge vs Local Potential
Qs ≈ √(20skTNA)[ys + eys-2yB)]1/2
Beyond threshold, all charge goes to inversion layer
How do we get the curvatures?
Add other terms and keep
Leading term
EXACT
Inversion Charge vs Gate voltage
Q ~ eys-2yB), ys- 2yB ~ log(VG-VT)
Exponent of a logarithm gives a linear variation of Qinv with VG
Qinv = -Cox(VG-VT)
Why Cox?
Questions
 What is the MOS capacitance? QS(yS)
 What are the local conditions during inversion?
 How does the potential vary with position?
yS,cr
y(x)
 How much inversion charge is generated at the surface? Qinv(x,yS)
 Add in the oxide: how does the voltage divide?
yS(VG), yox(VG)
 How much gate voltage do you need to invert the channel? VTH
 How much inversion charge is generated by the gate? Qinv(VG)
What’s the overall C-V of the MOSFET?
QS(VG)
Capacitance


 np0
 y
y
)
1

e

e

1




p
QS
S 
p0 

CD 

y
2LD

np0 

F  y S ,

p
p0 

s
s
For ys=0 (Flat Band):
2
3
x
x
x

 ........
Expand exponentials….. e  1  x 
2! 3!
S
CD (flat _ band) 
LD
ECE 663
Capacitance of whole structure
• Two capacitors in series:
Ci - insulator
CD - Depletion
1 1
1


C Ci CD
OR
Ci C D
C
Ci  CD
i
Ci 
d
ECE 663
Capacitance vs Voltage
ECE 663
Flat Band Capacitance
• Negative voltage = accumulation – C~Ci
V  0  y  0  C  CFB
• Zero voltage – Flat Band
i
d  LD
s
1
1
1
1
1  s d   i LD


 


CFB Ci CD  i  s
i s
i
d LD
 CFB
i

d   LD
i
s
ECE 663
CV
• As voltage is increased, C goes through minimum
(weak inversion) where dy/dQ is fairly flat
• C will increase with onset of strong inversion
• Capacitance is an AC measurement
• Only increases when AC period long wrt minority
carrier lifetime
• At “high” frequency, carriers can’t keep up – don’t
see increased capacitance with voltage
• For Si MOS, “high” frequency = 10-100 Hz
ECE 663
CV Curves – Ideal MOS
Capacitor
'
min
C
i

d   Wmax
i
s
ECE 663
But how can we operate gate at
today’s clock frequency (~ 2 GHz!)
if we can’t generate minority
carriers fast enough (> 100 Hz) ?
ECE 663
MOScap vs MOSFET
ECE 663
MOScap vs MOSFET
Gate
Insulator
Channel
Substrate
Minority carriers generated by
RG, over minority carrier lifetime
~ 100ms
So Cinv can be << Cox if fast gate
switching (~ GHz)
Gate
Insulator
Source
Channel
Drain
Substrate
Majority carriers pulled in
from contacts (fast !!)
Cinv = Cox
ECE 663
Example Metal-SiO2-Si
•
•
•
•
NA = 1017/cm3
At room temp kT/q = 0.026V
ni = 9.65x109/cm3
-14 F/cm
 NA 
s =411.9x1.85x10
 s kT ln

11.9 x8.85 x10 14 X 0.026ln1017
Wmax 
2
 ni  
q NA
9.65 x109 )
1.6 x10 19 X 1017
Wmax  10 5 cm  0.1mm
ECE 663
Example
• d=50
nm thickMetal-SiO
oxide=10-5 cm 2-Si
-14 F/cm
• i=3.9x8.85x10
3.9 x8.85 x10
Ci 
i
d
14

10
5
 6.9 x10 7 F / cm 2
 1017 
2kT  N A 
y s (inv )  2y B 
ln
  0.84Volts
  2 x0.026x ln
9
q
n
9
.
65
x
10
 i 


C
'
min
i
3.9 x8.85x10 14
8
2



9
.
1
x
10
F
/
cm
d   Wmax 5 x10 7  3.9 11.9)10 5
i
s
'
Cmin
 0.13
Ci
VTH
qN AWmax
1.6 x10 19 x1017 x10 5

 2y B 
 y s (inv )  0.23  0.84  1.07Volts
7
Ci
6.9 x10
ECE 663
Real MIS Diode: Metal(poly)• Work functions
of gate andMOS
semiconductor are
Si-SiO
2
NOT the same
• Oxides are not perfect
– Trapped, interface, mobile charges
– Tunneling
• All of these will effect the CV characteristic and
threshold voltage
ECE 663
Band bending due to work
function difference
VFB  fms
ECE 663
Function
• Work
qfs=semiconductor
work Difference
function =
difference between vacuum and Fermi level
• qfm=metal work function
• qfms=(qfm- qfs)
• For Al, qfm=4.1 eV
• n+ polysilicon qfs=4.05 eV
• p+ polysilicon qfs=5.05 eV
• qfms varies over a wide range depending on
doping
ECE 663
ECE 663
SiO2-Si Interface Charges
ECE 663
Standard nomenclature for Oxide charges:
QM=Mobile charges (Na+/K+) – can cause
unstable threshold shifts – cleanliness
has eliminated this issue
QOT=Oxide trapped charge – Can be anywhere
in the oxide layer. Caused by broken
Si-O bonds – caused by radiation damage
e.g. alpha particles, plasma processes,
hot carriers, EPROM
ECE 663
QF= Fixed oxide charge – positive charge layer
near (~2mm) Caused by incomplete
oxidation of Si atoms(dangling bonds)
Does not change with applied voltage
QIT=Interface trapped charge. Similar in origin
to QF but at interface. Can be pos, neg,
or neutral. Traps e- and h during device
operation. Density of QIT and QF usually
correlated-similar mechanisms. Cure
is H anneal at the end of the process.
Oxide charges measured with C-V methods
ECE 663
Effect of Fixed Oxide Charges
ECE 663
ECE 663
Surface Recombination
Lattice periodicity broken at surface/interface – mid-gap E levels
Carriers generated-recombined per unit area
ECE 663
Interface Trapped Charge • Surface states – Q
R-G centers caused by
IT
disruption of lattice periodicity at surface
• Trap levels distributed
ND
1 in band gap, with

Fermi-type distributed:
ND 1  g D e ( E E ) / kT
F
D
• Ionization and polarity will depend on
applied voltage (above or below Fermi level
ECE 663
Effect of Interface trapped
charge on C-V curve
ECE 663
a – ideal
b – lateral shift – Q oxide, fms
c – distorted by QIT
ECE 663
Non-Ideal MOS capacitor
C-V curves
• Work function difference and oxide
charges shift CV curve in voltage from
ideal case
• CV shift changes threshold voltage
• Mobile ionic charges can change
threshold voltage as a function of time –
reliability problems
• Interface Trapped Charge distorts CV
ECE 663
All of the above….
• For the three types of oxide charges
d

1
1


the CVVFBcurve
is
shifted
by
the
voltage

x
r
(
x
)
dx

oxide _ ch arg e

Ci  d 0
on the capacitor Q/C
VFB  fms 
Qf
 Qm  Qot )
Ci
• When work function differences and
oxide charges are present, the flat
ECE 663
Some important equations in the
inversion regime (Depth direction)
VT = fms + 2yB + yox
yox = Qs/Cox
Gate
Insulator
Source Channel
Qs = qNAWdm
Wdm = [2S(2yB)/qNA]
Drain
Substrate
x
VT = fms + 2yB + ([4SyBqNA] - Qf + Qm + Qot)/Cox
Qinv = Cox(VG - VT)
Electrical nature of ideal MS
contacts
n-type
p-type
M > S
rectifying
ohmic
M < S
ohmic
rectifying
131