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Tallinn University of Technology
Raimund Ubar
Computer Engineering
Department
Founded as engineering college in
1918, TTU acquired university
status in 1936.
TTU has about 9000 students and
1209
employees,
offering
engineering
and
economics
diploma studies, bachelor, master
and
doctorate
degree
programmes.
Academic part of the university is
organised into
 8 faculties,
 30 departments and 108
chairs,
 7 centres and
 9 affiliated institutions.
Research Topics
• Computer science: Decision Diagrams
• Test Pattern Generation
Hierarchical Approaches
Defect-Level Testing
• Simulation of Circuits and Systems
Fault Simulation (SAF, functional faults, delays)
Dynamic (multivalued) Simulation
• Built-In Self-Test
Hybrid BIST
Functional BIST
• Hardware accelerators for Fault Simulation
European projects
History (1992-2000):
• TEMPUS: Digital Design based on PLDs (1992-95)
• EUROCHIP (1993 -1996) - EUROPRACTICE (1996 -)
• PECO: EEMCN - East European Microelectronics Cooperation
Network (1993-96)
• COPERNICUS: FUTEG - Functional Test Generation (199497)
• ESPRIT: ATSEC - Advanced Test Generation and Testable
Design Methodology (1994-96)
• COPERNICUS: SYTIC - System Design Training (1996-98)
• COPERNICUS: VILAB - Microelectronics Virtual Laboratory for
Cooperation in Research (1998-2002)
Current European Projects
• FRAMEWORK V: REASON - Research and Training Action for
System On Chip Design (2002-2004)
• FRAMEWORK V: eVikings II - Establishment of the Virtual
Centre of Excellence for IST RTD in Estonia
• SOCRATES 2 Thematic Network Project THEIERE -Thematic
Harmonisation in Electrical and Information EngineeRing in
Europe
• SOCRATES 2 Thematic Network Project ECET - European
Computing Education and Training (2002-2004)
• EUROPRACTICE
Our Partners
TTU cooperates with
about 20-30 universities
KTH
LIU
TTU
Jonköping
USA:
Michigan U
Dresden
Costa Rica
Indonesia
Grenoble
Ilmenau
Darmstadt
Stuttgart
Torino
EastKharkov
and
MiddleEurope
Hierarchical Test Generation Tool
y1 y2
Logic Synthesis
Scripts
Design Compiler
(Synopsys Inc.)
Gate Level
Descriptions
RTL Model
(VHDL)
FU
Library
(VHDL)
FU
Library
(DDs)
y4
Test patterns

#0
1
R2
RTL DD
Model
Hierarchical ATPG
M2
0
2
SSBDD Models
of FUs
e
M3
b

IN
0
y3
*
d
0
y1
R1 + R 2
1
1
2
Modules or subcircuits
are represented as
word-level DD structures
3
IN + R2
IN
R1
y2
y4
c
+
M1

R2
SSBDD Synthesis
a
R1 
RTL DD
Synthesis
y3
0
1
R1* R2
IN* R2
R2 
Turbo-Tester Tool Set
Methods:
Levels:
Gate
Macro
Deterministic
Random
Genetic
Fault models:
Methods:
Stuck-at-faults
Stuck-opens
Delay faults
Single fault
Parallel
Deductive
Test
Generation
Design
Test
BIST
Simulation
Fault
Simulation
Fault
Location
Fault
Table
Fault
Diagnosis
Methods:
BILBO
CSTP
Store/Generate
Test
Optimization
Hybrid BIST for Multiple Cores
Embedded tester for testing multiple cores
Embedded Tester
C2670
Test
Controller
BIST
C3540
Test access
mechanism
BIST
Tester
Memory
BIST
C1908
BIST
C880
BIST
C1355
SoC
Optimized Multi-Core H-BIST
Pseudorandom test is carried out in parallel,
deterministic test - sequentially
Applet for Learning RT L Test
For learning
problems of RTlevel digital
design and test:
• Design of
data path and
control path
• Tradeoffs
between speed
& HW cost
• RT-level
simulation
• Fault
simulation
• Test
generation
• DFT and
BIST
Virtual Lab: Tool integration
Cooperation with Fh-IIS, DTU, LIU, IISAS, WUT
Behavioral level
VHDL description
(EAS/IIS)
1
2
High-level
synthesis
RTL VHDL
description
MOSCITO
USER
3
(EAS/IIS)
High-level
VHDL description
(EAS/IIS)
Commercial
CAD software
Logic
synthesis
7
Gate-level
EDIF
8 EDIF-ISCAS
Schematic
entry
converter(TTU)
VHDL-DD
converter(TTU)
4 EDIF-SSBDD
9 ISCAS-SSBDD
converter(TTU)
converter(TTU)
High-level DD
model
SSBDD model
5 Hierarchical
ATPG(TTU)
6
Turbo Tester
(TTU)
ISCAS
benchmarks
10
Test patterns exchange interface
DefGen
(IIN)
ISCASnetlist
11 University
software
Functional test
(EAS/IIS)
Proposal: Ingredients of SoC test
Functional test
(system test)
System-on-a-Chip
BIST, test control, test access
IP core
1. Functional test to test the system (WP1)
2. BIST, embedded test for IP cores (WP3)
Tallinn University of Technology
• WP1. High-level modeling and simulation
 Methods for automated generation of functional
test at the system-level for verification
purposes.
 We have previous experience in:
 High-level modeling and simulation
 High-level test pattern generation
 Design error identification at the logic level.
Tallinn University of Technology
• WP3. Setting up a Virtual IP library
 Solutions for automated synthesis of the test
infrastructure to IPs.
 Novel hybrid BIST strategies
 Functional BIST
 Web based e-learning tools for teaching IP test
standards like Boundary scan and P1500.
Artec Design Group
• Artec Design Ltd. founded in 1998 is a successful
Estonian SME empoying more than 30 people.
• In 2001, the company was selected to top ten in
the Central European Technology Fast list.
• The field of the Artec company is designing
hardware, ASICs, embedded software and factory
information systems.
• The company has been involved in a number of
national and European level research projects.
Artec Design Group
• VPNow: an IP core for cryptographic network
processing.
– It allows any system with PCI interface to connect
using the IPSec encryption standard.
– Possible to send new, ipv6 internet protocol packets via
existing ipv4 networks and vice-versa.
• A network-ready, full-function compact 486
motherboard with an award-winning Single
Component Computer MachZ.