Transcript Project D02209 - High Speed Digital Systems Laboratory

High Speed Digital Systems Lab
Project D02209:
FPGA Bridge between High Speed Channel & Ethernet
Characterization presentation
11/04/10
Supervisor: Mony Orbach
Students: Alex Blecherov
Eyal Ben Dov
Project Period: 2 semesters
High Speed Digital Systems Lab
Motivation
• Utilizing High-speed communication between devices
• Narrowing the gap between High-speed LAN (via FSB) and
External network (via Ethernet)
• Demand for reliable and fast communication
High Speed Digital Systems Lab
General Conception
• Assuming there are two different large networks – Internal
Fast Network and External Network (slower one), we wish
to create a mutual environment (accelerator) to provide the
ability to communicate between them with high rates.
High Speed Digital Systems Lab
Goals
• Design & implementation of high speed communication
bridge on Xilinx FPGA device (using SoPC)
• Allowing Local and External networks which operate with
different protocols and rates to communicate with each
other
• Achieving best transmission rate possible
• Explore and expertise a new FPGA work environment
High Speed Digital Systems Lab
Specifications
Hardware
• Xilinx Virtex-6 ML605 FPGA Evaluation Kit
Software
• ISE Design Suite Logic Edition Version 11.4
• ISIM / Modelsim
High Speed Digital Systems Lab
Possible Solutions
Solution 2
Solution 1
Local Fast Networks
Local Fast Networks
(up to 6 Gb/ps)
(up to 6 Gb/ps)
External
Network
(TCP/IP)
Bridge: Virtex 6
ML605 FPGA
External
Network
(TCP/IP)
Bridge: Virtex 6
ML605 FPGA
High Speed Digital Systems Lab
Chosen Solution
External
Network
(TCP/IP)
Bridge: Virtex
6 ML605 FPGA
Local Fast
Networks
(up to 6 Gb/ps)
High Speed Digital Systems Lab
Local Fast
Network
Test Bench Diagram
(up to 6 Gb/ps)
External
Network
(TCP/IP)
Bridge: Virtex
6 ML605 FPGA
High Speed Digital Systems Lab
Block Diagram
External
Network
(TCP/IP)
Local Fast Networks
(up to 6 Gb/ps)
Mem
Ethernet TCP/IP
FPGA
Ethernet Core
Fast Serial Bus
Memory
Mem
Mem
FPGA
FSB
FPGA
MicroBlaze
Fast Serial Bus
Fast Serial Bus
Mem
Bridge on FPGA
Fast Serial Bus
High Speed Digital Systems Lab
Work Flow
• Utilizing MicroBlaze IP core.
• Programming communications protocols
(TCP/IP and internal network Protocol),
and embedding them into MicroBlaze.
• Implementing 3 additional cores :
Ethernet, FSB, External Memory, which
will be used for communication (first 2
cores), and a buffer (the latter).
High Speed Digital Systems Lab
General Time Line
Semester A:
• Expertise ISE 11.4 and its tools (ChipScope etc).
• In depth self-study of TCP/IP protocol.
• Learning and operating MicroBlaze.
• Learning the IP Cores which will be implemented in the FPGA.
• Implementation of basic prototype of the bridge (basic channel).
Semester B:
• Programming the FPGA to work as a bridge between the 2 networks.
• Full Integration between the cores.
• Verification & validation of the bridge.
High Speed Digital Systems Lab
Detailed Time Line (Sem. A)
21/3-27/3
Acquiring basic knowledge of Virtex 6
family and ML605 FPGA
Acquiring basic knowledge of ISE and
its tools
Executing BIST on the FPGA
In depth self-study of TCP/IP protocol
Testing the IP cores which will be used
in the project.
Learning and operating MicroBlaze
Mid Semester Presentation
28/3-3/4
4/4-10/4
11/4-17/4
18/4-24/4
25/4-1/5
2/5-8/5