Transcript PCI and ISA Network cards

GROS
(GROS IS A ROUTING OPERATING SYSTEM)
Batch : 6
Guide :Sabitha . S
Hemant Pillai
Dean John Abraham
Krishnakumar.R
Phases
• I – Network Card Details & Booting
Procedure.
• II – Switching to Protected mode &
Interrupt handling
• III – Reception & Transmission of
packets.
PCI and ISA Network cards
• Two types of architectures - ISA & PCI
• ISA - 16 bit access . PCI - 32 bit access
• Started off with ISA cards, later shifted
to PCI cards.
• Difference of concern - IRQ conflicts.
• IRQ of ISA - Manually
• IRQ of PCI - PCI Bios decides.
Base Address Of ISA cards
• Base Addresses provided by Vendor. For
eg. 0x220, 0x240, 0x260 .
• Search these addresses by looking at
return value of ‘inb’ instruction.
• 0xff - no card, any other value - presence
of card .
Base Address of PCI cards
• PCI BIOS decides base address of PCI
cards.
• PCI BIOS : Address port - 0xCf8 and
Data port - 0xCfC .
• 256 - bytes for each PCI device.
• Network card - Device ID : 0x02.
• Base Addr. and IRQ in 256 bytes.
Hardware Address Calculation
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48 bit qty
Stored in PROM
It has offset from base address
Vendor provides this
We read the 48 bits
Booting Procedure
• Initially BIOS does POST .
• Checks the bootability of device (0x55
and 0xAA at bytes 511 and 512).
• Copies first 512 bytes to address location
0x7C00 and starts execution.
• GROS code here in assembly.
• Copies 20 sectors from floppy (Later
changed to 15)
Switching to Protected Mode
• All Intel processors start as 8086 (real
mode)
• Load dummy IDT and GDT.
• Set LSB of CR0.
• Jump to location 0.
• Start executing code previously copied
code.
Programming the 8259A
• 8259A is the PIC(Programmable
Interrupt Controller).
• There are 2 ports - 0x20 for Master &
0xA0 for Slave.
• 8259A is initialized by writing the
Initialization Command Words (ICW1 ICW4) & Operational Command Words
(OCW1 - OCW3).
• IRQ 2 is reserved for slave PIC
• 8 IRQ lines for a single PIC
Key Board & Console
• IRQ registered is 1.
• Key board input through port 0x60.
• The interrupt handler for interrupt 1 is
registered to keyb function.
• The character received is written to video
memory.
• Video memory starts at 0xb8000
Initialize the Network Card
• The Vendor has provided some standard
procedure for initialization.
• Initialization consists of specifying – type
of access, interrupts to be serviced start
page, stop page etc.
• Circular Q buffer ring.
• Receive and Transmit page is same.
• Switch to promiscous mode
• Enable interrupts.
Interrupt Capturing Of NIC
• Register the interrupts of network card
to interrupt handler ‘net’
• When interrupt comes control passes to
net.
• Phase I – Print character ‘0’ whenever
entering net.
• Phase II – Print the header info.
Format of Packet header
Physical layer
DHA SHA
PT
DHA – Destination Hardware Address : 6 bytes
SHA - Source Hardware Address : 6 bytes
PT - Packet type : 2 bytes
(IP or ARP)
• Read in the data from buffer offset we have
Format of Read Data
provided.
SZ
NXT ST
SZ – Size of the received packet : 2 bytes
NXT - Shows the next data starting : 1byte
ST - Status (0x01 for OK) : 1byte
• Switch to page 0 of remote buffer
• Read data from Data port.
Interrupt Acknowledgement
• Feed Interrupt acknowledge to Interrupt
register of NIC.
• Send EOI ( End Of Interrupt ) to 8259
Interrupt Controller.
Sending of Packet
• Mask all Interrupts ( This is to be done while
receiving also).
• Feed in where to send the packet, in the send
buffer (Offset).
• Send the packet to data port.
• Done By DMA .
• Tell card to send packet by feeding value to
command register.
• Tcpdump
Summary
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Network interface Card programming.
Booting procedure
Protected mode .
Interrupt Handling, Key board &
Console
• Initialization Reception & Transmission.
• Languages and tools used.