Transcript The Standard IEEE 1588

Synchronization over Ethernet
Standard for a Precision Clock Synchronization
Protocol according to IEEE 1588
Synchronous Ethernet according to ITU-T G.8261
Prof. Hans Weibel, Zurich University of Applied Sciences
[email protected]
© 2003-2008 ZHAW
Who is
ZHAW – Zurich University of Applied Sciences?
 The School of Engineering is a department of the Zurich
University of Applied Sciences (ZHAW)
 ZHAW‘s Institute of Embedded Systems has a strong
commitment to industrial communications in general and to
Ethernet in particular, e.g.
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Real-time Ethernet (Ethernet Powerling, ProfiNet, etc.)
Synchronization (IEEE 1588)
High-availability Ethernet add-ons (MRP, PRP, etc.)
 The related R&D activities and services include
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Hardware assistance and off-load (IP)
Protocol stacks
Support
Engineering and consultancy
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 2
Preliminary remark
 only Ethernet solutions are taken into account in
this presentation (according to workshop planning)
 this requires some compromises to be accepted
 the big advantage to be exploited is that the same
infrastructure can be used for both data
transmission and synchronization
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 3
The Standard IEEE 1588
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 4
The Standard IEEE 1588
PTP Message Exchange
Master Clock
Delay
and
Jitter
Protocol
Stack
Slave Clock

PTP
PTP
UDP
UDP
optional
IP
IP
MAC
MAC
MII
MII
Phy
Delay
and
Jitter
Protocol
Stack
Phy
Network
PTP
UDP
IP
MAC
Phy
Precision Time Protocol (Application Layer)
User Datagram Protocol (Transport Layer)
Internet Protocol (Network Layer)
Media Access Control
Physical Layer
Delay and Jitter
Network
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 5
The Standard IEEE 1588
Determination of Phase Change Rate (Drift) – one step
Master Clock
Slave Clock
40
38
42
40
44
42
t0 k
46
44
48
46
50
Δ0
48
52
t1k
50
Δ0 = t0k+1 - t0 k
54
52
t0k+1
56
54
Δ1
58
Δ1 = t1k+1 - t1 k
56
60
58
62
60
64
t1k+1
Drift =
Δ1 -Δ0
Δ1
62
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 6
The Standard IEEE 1588
Determination of Phase Change Rate (Drift) – two step
Master Clock
Slave Clock
40
38
42
40
44
42
t0 k
46
44
48
46
50
Δ0
48
52
t1k
50
Δ0 = t0k+1 - t0 k
54
52
t0k+1
56
54
Δ1
58
Δ1 = t1k+1 - t1 k
56
60
58
62
60
64
t1k+1
Drift =
Δ1 -Δ0
Δ1
62
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 7
The Standard IEEE 1588
Determination of Delay and Offset
Master Clock
Slave Clock
40
O = Offset = ClocksSlave – ClocksMaster
38
42
40
44
42
t0
O
46
44
48
46
50
48
52
A
D = Delay
t1 = t0+D+O
measured values t0, t1, t2, t3
A = t1-t0 = D+O
50
54
52
56
54
B
B = t3-t2 = D-O
t2
Delay D = A + B
2
A-B
Offset O =
2
58
56
t3
60
58
62
60
64
62
t3 = t2-O+D
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 8
The Standard IEEE 1588
Boundary Clock copes with the Network‘s Delay Fluctuations
Master Clock

Switch with Boundary Clock

Slave
Master
Slave Clock

PTP
PTP
PTP
PTP
UDP
UDP
UDP
UDP
IP
IP
IP
IP
MAC
MAC
MAC
MAC
Phy
Phy
Phy
Phy
Switching Function
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 9
The Standard IEEE 1588
Topology and „Best Master Clock“
M
Ordinary Clock, Grandmaster: clock
selected as „best Master“ (selection based
on comparison of clock descriptors)
S
M M M
S
S
S
S
Boundary Clock, e.g. Ethernet switch
S: Port in Slave State
M: Port in Master State
S
M M M
S
Ordinary Clock
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 10
The Standard IEEE 1588 Version 2
Transparent Clock
Slave Clock
Master Clock
Transparent Clock
Sync(t0 , corr)
t0
Δs
Sync(t0 , corr + Δs)
t1
Follow_up(t0)
Delay_Req(corr)
Delay_Req(corr + Δr)
t
t2
Δr
3
Time Stamping
Delay_Resp(t3 , ∑corr)
Δ
t
Residence Time
t
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 11
The Standard IEEE 1588 Version 2
Transparent Clock – End-to-End Delay Measurement
S
TC
M
S
TC
TC
TC
S
S
S
Sync Stream
e2e Delay Measurement
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 12
The Standard IEEE 1588 Version 2
Transparent Clock – Peer-to-Peer Delay Measurement
S
TC
M
S
TC
TC
TC
S
S
S
Sync Stream
p2p Delay Measurement
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 13
The Standard IEEE 1588
Limits
 Timestamp quantization effects
 Accuracy of Start-of-Frame Detection
 Unknown portion of data path asymmetries in cables and transceivers
 Jitter in the data path (PHY chips, network elements)
 Environmental conditions
 Oscillator instabilities
 Implementation specific effects (e.g. phase between different
asynchronous clock domains of all involved functional building blocks)
 Note: Uncertainty due to limited observation capabilities (e.g. the PPS
output is subject of quantization effects as well)
 Stochastic effects can be filtered out with statistical methods
 Systematic errors remain
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 14
The Standard IEEE 1588
Industry Relevance
 PTP is or will be applied in application areas such as
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Test and Measurement (LXI: LAN eXtensions for Instrumentation)
Automation and control systems (various flavors of real-time Ethernets)
Audio/Video Bridge (AVB according to IEEE 802.1as)
Telecommunications
 Silicon vendors and IP providers offer
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Protocol software
Hardware assistance IPs
PHYs with hardware assistance logic
IEEE-1588 enabled microcontrollers
Switching cores with IEEE-1588 support
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 15
Synchronous Ethernet
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 16
Synchronous Ethernet
Physical Layer Timing in Legacy Ethernet
 Ethernet works perfectly well with relatively inaccurate clocks
 Each Ethernet link may use its own clock

nominal clock rate is the same, but deviations of ± 50 ppm are allowed
(dimensioning such that physical layer buffers do not underflow or overflow)
 Details differ according to transmission technology
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where the two directions of a link use different media (i.e. separate wire pairs
or separate fibers), both directions may have independent clocks
GBE over twisted pair uses all wire pairs simultaneously in both directions
 signal processing (echo compensation technique) requires same clock on
both directions of a link
 one PHY acts as the master, the other as slave
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 17
Synchronous Ethernet
Timing of a Fast Ethernet Link (100 Base-TX)
25 MHz ± 50 ppm
MAC
PHY
PHY
TX_CLK
MAC
RX_CLK
Cable
TX_CLK
RX_CLK
Symbol
clk
25 MHz ± 50 ppm
clk
transmission line
is driven by clk
clk recovered from
transmission line
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 18
Synchronous Ethernet
Physical Layer Timing in Legacy Ethernet
E
X
E
E
X
X
E
X
E
E
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 19
Synchronous Ethernet
Timing of a Gigabit Ethernet Link (1000 Base-T)
 1000 Base-T transmission is split on 4 wire pairs operation simultaneously in
both directions
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transmitter and receiver are coupled via a hybrid
echo compensation is applied
both directions require the same clock
 A 1000 Base-T PHY can operate as a master or slave.
 Master/slave role selection is part of the auto-negotiation procedure.
 A prioritization scheme determines which device will be the master and which
will be slave.
 The supplement to Std 802.3ab, 1999 Edition defines a resolution function to
handle any conflicts:
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multiport devices have higher priority to become master than single port devices.
if both devices are multiport devices, the one with higher seed bits becomes the
master.
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 20
Synchronous Ethernet
1000 Base-T uses 4 pairs simultaneously in both directions
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 21
Synchronous Ethernet
1000 Base-T Pysical Layer Signalling with Echo Compensation
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 22
Synchronous Ethernet
Timing of a Gigabit Ethernet Link (1000Base-T)
25 MHz ± 50 ppm
MAC
PHY
GTX_CLK
Master
CLOCK_IN
PHY
Slave
x5
MAC
RX_CLK
Cable
RX_CLK
GTX_CLK
25 MHz ± 50 ppm
 The Master PHY uses the internal 125 MHz clock generated from CLOCK_IN to
transmit data on the 4 wire pairs.
 The Slave PHY uses the clock recovered from the opposite PHY as the transmit clock.
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 23
Synchronous Ethernet
Concept - 1
 Concept has been proposed, elaborated, and standardized by the Telco
community in ITU-T by transferring the traditional SDH clock
distribution concept to Ethernet networks
 The Primary Reference Clock (PRC) frequency is distributed on the
physical layer
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a receiver can lock to the transmitter‘s frequency
a switch selects the best available clock
this results in a hierarchical clock distribution tree
 OAM messages (Synchronization Status Messages) are used to signal
clock quality and sync failure conditions of the upstream switch
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to allow selection of the best available timing source (stratum of upstream
source)
to avoid timing loops
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 24
Synchronous Ethernet
Concept - 2
 Active layer 2 data forwarding topology (as established by spanning tree
protocol) and clock distribution tree are independent (i.e. a blocked port
can deliver the clock to its neighboring switch)
 Design rules (topology restrictions, priorities for source selection)
guarantee clock quality
 Clocking of Ethernet devices is changed in a way that is fully conforming
with IEEE 802.3 standards
 Standard PHY chips can be used as long as a few conditions are met, e.g.
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PHY provides the recovered receive clock to the external world
GBE PHY allows master/slave role to be set by software (no automatic
selection)
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 25
Synchronous Ethernet
Clock Sources for a Synchronous Ethernet Switch
Ext-In
Ext-Out
Oscillator
Clock Selection / Regeneration
Port 1
Port 2
Port …
Port n
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 26
Synchronous Ethernet
Physical Layer Timing in Synchronous Ethernet
E
PRC
X
E
E
X
X
E
X
PRC tracable
clock (other links
and directions are
free running)
E
E
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 27
Synchronous Ethernet
Compared with IEEE 1588
Synchronous Ethernet
IEEE 1588
 Clock distribution based on
Ethernet‘s physical layer
 Application layer protocol with
hardware assistance
 Provides frequency only
 Provides frequency and time of day
 Performance is independent of data
traffic
 May be susceptible to specific data
traffic patterns
Complementary technologies, can be used in combination:
Syncronous Ethernet delivers accurate and stable frequency
to all nodes while IEEE 1588 can deliver time of day, where
required.
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 28
Synchronous Ethernet
Industry Relevance
 Telco equipment manufacturers rely on both technologies
 Synchronous Ethernet operation will certainly be an important feature in
future carrier grade products
 Synchronous Ethernet’s role in corporate and industrial communication
application is not yet forseeable
 Silicon vendors and IP providers offer
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Synchronous Ethernet compatible PHYs
ICs for clock monitoring, selection, and processing
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 29
Many thanks for your attention!
[email protected]
Zurich University of Applied Sciences
Institute of Embedded Systems
http://ines.zhaw.ch/ieee1588
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 30