Transcript Document
Active System Area Networks (ASAN)
Dr. Ken Mackenzie, Dr. David Schimmel, Dr. Sudhakar Yalamanchili
Chris Clark, Adam Johnson, Craig Ulmer, Chris Wood
Concept
Streaming Computations
Streaming Details
Perform computations on messages in-transit
FPGAs process data at link speeds
Advantage: Usable by CPUs and peripheral devices
Examples: Data transformations, Cryptography, Filtering
CPU
CPU
Computation
1
Video
Capture
Computation
2
CPU
Media
Processor
Media
Processor
NI
CPU
Media
Processor
NI
NI
FPGA
NI
NI
Computational
Circuit 1
System Area Network
FPGA Reconfiguration
FPGA
FPGA
Circuit 2
Circuit 3
NI
NI
CPU
FPGA
FPGA
Configuration
FPGA
Forwarding Directory
Destination: Host
Computational Circuits
AM: Receive FFT
Circuit 1:
Computational
Circuit N
FFT
NI-FPGA Prototypes
FPGA Interfaces
SRAM
0
SRAM
1
SRAM
2
SRAM
3
Control & Switching
FPGA
Tx
Myrinet
NI
Rx
E
1
Tx
E
2
Rx
E
3
E
4
SRAM
Tx
E
5
E
6
FPGA
PMC
PMC
SRAM/
SDRAM
PCI
Strong
Arm
PCI
RC-1000
FPGA
Input
Queues
Output
Queues
Communication Library API
Application
Data
Memory API
FPGA Control
User Circuit API
Intel IXP 1200
User Circuit 1
Configuration
Previous Work:
Celoxica RC-1000
Myricom Myrinet
Current Work:
Intel IXP 1200
Xilinx Virtex II FPGA
User Circuit n
FPGA Circuit Canvas
FPGA
Classify IP packets
FPGA Example: Cryptography
Cryptography unit
Inputs
DES, RC6, MD5, ALU
Keys set dynamically
73 MB/s for 4KB data
Conclusions and Future Work
Control Block
20%
Unused
30%
Binary Decision Diagram
ALU
5%
DES
6%
MD5
26%
RC6
13%
Full reconfiguration approach
0 1
Out Message
Circuit N: Encrypt
CPU
1
Destination: FPGA
Forward Entry: X
AM: Perform FFT
FPGA
NI
System Area Network
Rx
FPGA Example: Pattern Matching for
Packet Classification
Outputs are classification
Map BDD to FPGA gates
Muxes and registers
FPGA
In Message
FPGA Card Memory
Currently: Full FPGA reconfiguration
Research: Partial run-time reconfiguration
Pattern matching task
Implement in FPGA
Forwarding: Where are results sent?
Programmable forwarding directory
Physical Model
Demand driven dynamic reconfiguration
Host manages FPGA configurations
Requested circuit not loaded?
FPGA stores state,
generates function fault
Host loads new configuration
FPGA loads state, restarts
Computation
N
Conceptual Model
CPU
CPU
Video
Capture
CPU
Computation: Which computation performed?
Active message approach
01
Classifications
0
Configure time: 90 ms
Possible to create optimized key-specific configurations
FPGAs valuable for network processing
Perform custom computations in hardware
Adaptable to different problems
ASAN allows computations to take place in network
Processing in NI and peripheral devices
Powered by GRIM communication library
Future work
Partial FPGA reconfiguration mechanisms
Selectable computation target (Host, NI, or FPGA)
Transition to IXP based Gigabit Ethernet