Transcript 360N: Computer Architecture Spring 2005

RAMP-White
Derek Chiou
The University of Texas at Austin
© Derek Chiou
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Test of size
High Level Characteristics
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Coherent distributed shared memory machine
Scalable at the same level as other RAMP machines
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Intended to be ISA/Architecture independent
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Use different cores
All RAMP efforts are intended to be ISA independent
Intended to integrate components from other RAMP
participants
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7/17/2015
1K eventual target
A testbed for sharing of IP
RAMP-White
2
Test of size
Our Additions
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New code in Bluespec rather than Verilog/VHDL
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Embedded PowerPC as one core
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7/17/2015
More configurable
That’s what my group is using
Leon decided on after we started, just recently boots Debian
Wanted to determine issues of different cores
My research needs fast cores
Eventually an SMP OS, initially multi-OS shared space
initially
RAMP-White
3
Test of size
Issues
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Architecture
Implementation
Operating System
Sharing IP
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7/17/2015
Language
Maturity
Infrastructure (CVS, etc.)
RAMP-White
4
Test of size
Three Stages (for Implementation Ease)
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Incoherent shared memory
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No hardware global cache, just global shared memory support
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However, software can maintain coherence if necessary
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Requires a coherent cache
Running essentially a snoopy protocol
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True coherence engine not required
But, very restricted communication
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Good for testing, modeling many targets
General network-based coherence
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7/17/2015
Network virtual memory
Run a simulator on top of the processor
Ring-based coherence (scalable bus)
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Optimal cache for local memory
Requires general coherence engine
RAMP-White
5
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Generalized Architecture
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ISA dependent
Intersection Unit
Network Interface Unit
Proc
$
Mem MC
PLB
IU
NIU ISA independent
OPB
bridge
7/17/2015
RAMP-White
6
Test of size
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Intersection Unit
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Sits between the Processor
(cache), PLB bus and NIU
Processor interface
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Proc
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Network interface
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$
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Mem MC
IU
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NIU
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Incoherent version is a special case
Programmable regions
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7/17/2015
Master
Eventually snoop
Hooks for coherency engine
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OPB
bridge
Master
Slave
Memory interface
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PLB
Slave
Eventually snoop
RAMP-White
Global (local and remote)
Local
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Test of size
Network Interface Unit
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Proc
Split into two components
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Msg composition/Queuing
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Net transmit/receive
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Insert/extract for ring
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Intended to permit other
transmit/receive
$
Mem MC
PLB
IU
NIU
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One input/one output
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OPB
bridge
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7/17/2015
RAMP-White
Creates a simple
unidirectional ring
Can interface to more
advanced fabrics
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Test of size
Operating System
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Started by looking at PowerPC
Wanted an SMP OS
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Knew we didn’t have coherent cache
But, also missing TLB Invalidation & OpenPIC (interprocessor
interrupts, bring-up)
But, do have load-reservation/store-conditional instructions
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Leon is SMP-capable, so should avoid these issues
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Starting with separate OS’s
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Region of memory is global
(no Block Address Translation (BAT) so need to manage global
pages)
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7/17/2015
mmap
RAMP-White
9
Test of size
Status: Hari Angepat
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Bluespec learned
NIU code complete and unit tested
IU code complete being tested on XUP
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2 PowerPC processors
Supports interfaces
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Processor Slave
PLB Master
NIU
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Hardware intended to target different ISAs
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Some preliminary OS work
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Targets Phase 1 (incoherent shared memory)
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7/17/2015
SMP-linux investigation
Multi-image mmap interface currently targeted
2 IUs, 1 MC with an arbiter
RAMP-White
10
Test of size
Our Long Term Plans
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Phase 1, XUP complete end of 1Q07
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Phase 2, 1 BEE2 board hopefully will be 2Q07
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Larger scalability, BEE2, Berkeley MC, Leon?, RDL?
Phase 3, hopefully 4Q07
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With multi-OS support (with help from Stanford?)
Arbitrary network, cache coherency engine, SMP OS?, Leon?, RDL?
x86 CMP/SMP on top of RAMP-White
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Full cycle accurate (separate timing model)
RAMP-White executes functional model in parallel
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Start with Phase 1 (separate team)
For Phase 3, tie target coherence system to RAMP-White
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7/17/2015
Heterogeneous hosts!
Cache maintained by target coherence, not by host coherence
RAMP-White
11
Test of size
Sharing IP: Some Preliminary Experience
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We looked at RAMP-Red XUP
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Used some code (PLB master)
Red-BEE is not ready to distribute
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Looking for switch code
Berkeley’s code on CVS repository
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But, we can’t use memory controller because we don’t have BEE2 board yet
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Bluespec
We are spinning almost all of our own code right now
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Would like to steal software
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Naming
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7/17/2015
OS (kernel proxy)
SMP OS port
MPI reference design in BEE2 repository
Is that RAMP-Blue?
A central CVS repository for RAMP code?
RAMP-White
12
Test of size
Sharing Over the Long Term
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Processor is shared
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Proc
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MC is shared
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$
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IU
NIU
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RAMP-White
Borrow half from Berkeley?
Network can be shared
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7/17/2015
Trying to make ours general
NIU can be shared
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CMU/Stanford
IU functionality can be shared
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Peripherals
Transactional/traditional
Borrow Stanford’s?
Coherency engine can be shared
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CCE
Xilinx or Berkeley
Coherent cache can be shared
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Mem MC
Leon
PowerPC
MicroBlaze
Everything else
Borrow Berkeley’s?
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Test of size
Conclusions
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RAMP White is started
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7/17/2015
Hari has been working full time for 1 semester
Have a clear first direction
Architecture looks fairly flexible
Would like to discuss how to share IP better so we
don’t reinvent the wheel
RAMP-White
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