Transcript Presentation Title Here - keystone-workshop

KeyStone SoC
Architecture Overview
KeyStone Training
Multicore Applications
Literature Number: SPRP816
Agenda
• KeyStone I Architecture
–
–
–
–
–
CorePac & Memory Subsystem
Internal Communications and Transport
External Interfaces
Coprocessors and Accelerators
Miscellaneous
• KeyStone II Architecture
– ARM Cortex-A15 CorePac
– Performance/Throughput Improvements
• KeyStone Platform
– Debug
– Device-Specific Offerings
2
KeyStone I Architecture
•
•
•
•
•
CorePac & Memory Subsystem
Internal Communications and Transport
External Interfaces
Coprocessors and Accelerators
Miscellaneous
KeyStone I Device Architecture
Application-Specific
Coprocessors
Memory Subsystem
C66x™
CorePac
Miscellaneous
HyperLink
TeraNet
Multicore Navigator
External Interfaces
Network Coprocessor
4
KeyStone I CorePac
Application-Specific
Coprocessors
Memory Subsystem
C66x™
CorePac
L1D
L1P
Cache/RAM Cache/RAM
L2 Memory Cache/RAM
Miscellaneous
HyperLink
1 to 8 Cores @ up to 1.25 GHz
TeraNet
Multicore Navigator
External Interfaces
Network Coprocessor
• 1 to 8 C66x CorePac DSP Cores
operating at up to 1.25 GHz
– Fixed- and floating-point
operations
– Code compatible with other
C64x+ and C67x+ devices
• L1 Memory
– Can be partitioned as cache
and/or RAM
– 32KB L1P per core
– 32KB L1D per core
– Error detection for L1P
– Memory protection
• Dedicated L2 Memory
– Can be partitioned as cache
and/or RAM
– 512 KB to 1 MB Local L2 per core
– Error detection and correction
for all L2 memory
• Direct connection to memory
5
subsystem
KeyStone I Memory Subsystem
Memory Subsystem
DDR3 EMIF
MSM
SRAM
Application-Specific
Coprocessors
MSMC
C66x™
CorePac
L1D
L1P
Cache/RAM Cache/RAM
L2 Memory Cache/RAM
Miscellaneous
HyperLink
1 to 8 Cores @ up to 1.25 GHz
TeraNet
Multicore Navigator
External Interfaces
Network Coprocessor
• Multicore Shared Memory (MSM SRAM)
• 1 to 4 MB
• Available to all cores
• Can contain program and data
• All devices except C6654
• Multicore Shared Memory Controller (MSMC)
• Arbitrates access of CorePac and SoC
masters to shared memory
• Provides a connection to the DDR3 EMIF
• Provides CorePac access to coprocessors and
IO peripherals
• Provides error detection and correction for
all shared memory
• Memory protection and address extension
to 64 GB (36 bits)
• Provides multi-stream pre-fetching
capability
• DDR3 External Memory Interface (EMIF)
• Support for 16-bit, 32-bit, and (for C667x
devices) 64-bit modes
• Specified at up to 1600 MT/s
• Supports power down of unused pins when
using 16-bit or 32-bit width
• Support for 8 GB memory address
6
• Error detection and correction
Enhanced DMA: EDMA3 1D Transfer
DDR
EDMA
Transfer
Controller
1D transfer is used to move a vector.
L2
EDMA3: 2D Transfer
DDR
EDMA
Transfer
Controller
2D transfer is used to move a matrix; That is, to share a
frame between multiple cores.
L2
EDMA3: 3D Transfer
DDR
EDMA
Transfer
Controller
3D transfer is used to move multiple matrices. That is,
to share frames between multiple cores.
L2
EDMA3: Transfer 2D Destination
DDR
EDMA
Transfer
Controller
It is faster to have strides in SRAM (like L2) than in DDR, so that it reads a
complete line and distributes between L2 memories.
L2
Core 0
L2
Core 1
L2
Core 2
L2
Core 3
EDMA3: Source and Destination
Matrix transport is used to turn rows into columns.
Based on the direction, use 2D in the source (Shared L2
to DDR) or the destination (DDR to Shared L2).
KeyStone I Multicore Navigator
Memory Subsystem
DDR3 EMIF
MSM
SRAM
Application-Specific
Coprocessors
MSMC
C66x™
CorePac
L1D
L1P
Cache/RAM Cache/RAM
L2 Memory Cache/RAM
Miscellaneous
HyperLink
1 to 8 Cores @ up to 1.25 GHz
TeraNet
Multicore Navigator
Queue
Packet
Manager
DMA
External Interfaces
Network Coprocessor
• Provides seamless inter-core
communications (messages
and data exchanges) between
cores, IP, and peripherals.
“Fire and forget”
• Low-overhead processing and
routing of packet traffic to and
from peripherals and cores
• Supports dynamic load
optimization
• Data transfer architecture
designed to minimize host
interaction while maximizing
memory and bus efficiency
• Consists of a Queue Manager
Subsystem (QMSS) and
multiple, dedicated Packet
DMA (PKTDMA) engines 12
KeyStone I Network Coprocessor
Application-Specific
Coprocessors
Memory Subsystem
DDR3 EMIF
MSM
SRAM
MSMC
C66x™
CorePac
L1D
L1P
Cache/RAM Cache/RAM
L2 Memory Cache/RAM
TeraNet
External Interfaces
Switch
Multicore Navigator
Queue
Packet
Manager
DMA
Ethernet
Switch
HyperLink
1 to 8 Cores @ up to 1.25 GHz
SGMII
x2
Miscellaneous
Security
Accelerator
Packet
Accelerator
Network Coprocessor
• Provides hardware accelerators to
perform L2, L3, and L4 processing
and encryption that was previously
done in software
• Packet Accelerator (PA)
• Single or multiple IP address
option
• UDP (and TCP) checksum and
selected CRCs
• L2/L3/L4 support
• Quality of Service (QoS)
• Multicast to multiple
destinations inside the device
• Timestamps
• Security Accelerator (SA)
• Hardware encryption,
decryption, and
authentication
• Supports IPsec ESP, IPsec AH,
SRTP, and 3GPP protocols 13
KeyStone I External Interfaces
Application-Specific
Coprocessors
Memory Subsystem
MSM
SRAM
DDR3 EMIF
MSMC
C66x™
CorePac
L1D
L1P
Cache/RAM Cache/RAM
L2 Memory Cache/RAM
1 to 8 Cores @ up to 1.25 GHz
Miscellaneous
TeraNet
HyperLink
Switch
Ethernet
Switch
SGMII
x2
x4
SRIO
Device
Specific I/O
SPI
UART
x2
PCIe
I2C
GPIO
Device
Specific I/O
Multicore Navigator
Queue
Packet
Manager
DMA
Security
Accelerator
Packet
Accelerator
• 2x SGMII ports support
10/100/1000 Ethernet
• 4x high-bandwidth
Serial RapidIO (SRIO) lanes
• 2x PCIe at 5 Gbps
• SPI for boot operations
• UART for
development/testing
• I2C for EPROM at 400 Kbps
• GPIO
• Device-specific Interfaces
– Wireless Applications
– General Purpose
Applications
Network Coprocessor
14
TeraNet Switch Fabric
Application-Specific
Coprocessors
Memory Subsystem
MSM
SRAM
DDR3 EMIF
MSMC
C66x™
CorePac
L1D
L1P
Cache/RAM Cache/RAM
L2 Memory Cache/RAM
1 to 8 Cores @ up to 1.25 GHz
Miscellaneous
TeraNet
HyperLink
Switch
Ethernet
Switch
SGMII
x2
x4
SRIO
Device
Specific I/O
SPI
UART
x2
PCIe
I2C
GPIO
Device
Specific I/O
Multicore Navigator
Queue
Packet
Manager
DMA
Security
Accelerator
Packet
Accelerator
• A non-blocking switch fabric
that enables fast and
contention-free internal data
movement
• Provides a configured way –
within hardware – to manage
traffic queues and ensure
priority jobs are getting
accomplished while minimizing
the involvement of the CorePac
cores
• Facilitates high-bandwidth
communications between
CorePac cores, subsystems,
peripherals, and memory
Network Coprocessor
15
KeyStone I TeraNet Data Connections
S
M
TPCC
TC0 M
16ch QDMA TC1 M
EDMA_0
S DDR3
CPUCLK/2
256bit TeraNet
HyperLink
HyperLink
S Shared L2
S S S S
XMC
SRIO
L2
0-3 M
M
SS Core
Core
S
M
S Core M
M
M
Network M
Coprocessor
S
TAC_FE
M
M
M
M
M
RAC_BE0,1
RAC_BE0,1 MM
FFTC / PktDMA M
FFTC / PktDMA M
AIF / PktDMA M
QMSS
M
PCIe
M
DebugSS
SRIO
CPUCLK/3
128bit TeraNet
TC2 M
TPCC
M
TC6
TPCC TC3
64ch
TC4TC7
M
64ch
QDMA TC5TC8
M
QDMA TC9
EDMA_1,2
S TCP3e_W/R
S
M
MSMC
M
DDR3
• Facilitates high-bandwidth
communication links
between DSP cores,
subsystems, peripherals, and
memories.
• Supports parallel orthogonal
communication links
TCP3d
TCP3d
S
S TAC_BE
S
S
RAC_FE
RAC_FE
S SVCP2
(x4)
(x4)
SVCP2
SVCP2
VCP2(x4)
(x4)
S
QMSS
S
PCIe
M
16
KeyStone I HyperLink Bus
Application-Specific
Coprocessors
Memory Subsystem
MSM
SRAM
DDR3 EMIF
MSMC
Debug/Trace
C66x™
CorePac
• Provides the capability to
expand the device to include
hardware acceleration or
other auxiliary processors
• Supports four lanes with up to
12.5 Gbaud per lane
L1D
L1P
Cache/RAM Cache/RAM
L2 Memory Cache/RAM
1 to 8 Cores @ up to 1.25 GHz
Miscellaneous
TeraNet
HyperLink
Switch
Ethernet
Switch
SGMII
x2
x4
SRIO
Device
Specific I/O
SPI
UART
x2
PCIe
I2C
GPIO
Device
Specific I/O
Multicore Navigator
Queue
Packet
Manager
DMA
Security
Accelerator
Packet
Accelerator
Network Coprocessor
17
KeyStone I Miscellaneous Elements
Application-Specific
Coprocessors
Memory Subsystem
MSM
SRAM
DDR3 EMIF
MSMC
Debug/Trace
Boot ROM
Semaphore
C66x™
CorePac
Power
Management
PLL
L1D
L1P
Cache/RAM Cache/RAM
x3
L2 Memory Cache/RAM
EDMA
1 to 8 Cores @ up to 1.25 GHz
x3
TeraNet
HyperLink
Switch
Ethernet
Switch
SGMII
x2
x4
SRIO
Device
Specific I/O
SPI
UART
x2
PCIe
I2C
GPIO
Device
Specific I/O
Multicore Navigator
Queue
Packet
Manager
DMA
• Boot ROM
• Semaphore module provides
atomic access to shared chiplevel resources.
• Power Management
• Three on-chip PLLs:
– PLL1 for CorePacs, except
– PLL2 for DDR3
– PLL3 for Packet
Acceleration
• Three EDMA controllers
• Eight 64-bit timers
• Inter-Processor
Communication (IPC) Registers
Security
Accelerator
Packet
Accelerator
Network Coprocessor
18
KeyStone Central Interrupt Controller
C66x
CorePac0
CIC0
C66x
CorePac1
C66x
CorePac2
C66x
CorePac3
C66x
CorePac4
Events
C66x
CorePac5
CIC1
C66x
CorePac6
C66x
CorePac7
HyperLink
EDMA CC0
EDMA CC1
CIC2
EDMA CC2
EDMA CC3
EDMA CC4
Peripherals
ARM A15
CorePac
19
Diagnostic Enhancements
Application-Specific
Coprocessors
Memory Subsystem
MSM
SRAM
DDR3 EMIF
MSMC
Debug/Trace
C66x™
CorePac
L1D
L1P
Cache/RAM Cache/RAM
L2 Memory Cache/RAM
1 to 8 Cores @ up to 1.25 GHz
Miscellaneous
TeraNet
HyperLink
Switch
Ethernet
Switch
SGMII
x2
x4
SRIO
Device
Specific I/O
SPI
UART
x2
PCIe
I2C
GPIO
Device
Specific I/O
Multicore Navigator
Queue
Packet
Manager
DMA
Security
Accelerator
Packet
Accelerator
• Embedded Trace Buffers (ETB)
enhance the diagnostic
capabilities of the CorePac.
• CP Monitor enables diagnostic
capabilities on data traffic
through the TeraNet switch
fabric.
• Automatic statistics collection
and exporting (non-intrusive)
• Monitor individual events for
better debugging
• Monitor transactions to both
memory end point and
Memory-Mapped Registers
(MMR)
• Configurable monitor filtering
capability based on address
and transaction type
Network Coprocessor
20
KeyStone II Architecture
• ARM Cortex-A15 CorePac
• Performance/Throughput Improvements
Keystone II Architecture Example
KeyStone II Device Architecture
C66x CorePac
ARM A15 CorePac
Memory Subsytem
Multicore Navigator
Network Coprocessor
TeraNet Switch Fabric
10 Gigabit Ethernet (10 GBE)
External Interfaces
HyperLink Bus
Miscellaneous
23
ARM Cortex-A15 CorePac
• Single, Dual, or Quad-ARM A15 CorePac
operating at up to 1.4 GHz.
– Full implementation of ARMv7-A
architecture instruction set
– Integrated Neon and Vector
Floating-Point Unit
• L1 Memory: 32KB L1 per ARM A15 for
caching program and data
• L2 Memory:
– Shared L2 Cache Memory with full cache
coherency using Snoop Control Unit (SCU)
– 4 MB L2 Cache is shared between the 1 to
4 ARM A15 core(s).
• The AMBA 4.0 AXI Coherency Extension
(ACE) master port is connected directly to
the MSMC2 for short-path access to shared
MSMC SRAM.
• The ACE also provides IO-coherent access
to the shared memory and external
memory connected through the EMIF.
• Cluster-level and core-level power
management and low-power standby
modes (also known as WFI/WFE modes) 24
KeyStone II Memory Subsystem: MSM/MSMC
• Multicore Shared Memory (MSM SRAM)
– 2-6 MB shared among the C66x and
ARM A15 CorePacs.
– May contain program and data
• Multicore Shared Memory Controller
(MSMC version 2.0)
– Arbitrates access of C66x and ARM
A15 CorePac and SoC masters to
shared and external memory through
DDR3 EMIF
– Provides error detection and
correction for all shared memory
– Memory protection and address
extension to 64 GB (36 bits)
– Provides multi-stream pre-fetching
capability
– Support for ARM coherency with
EDMA/peripheral masters in DDR3A
and MSMC SRAM space
– 8 SRAM banks
– Runs at the DSP frequency, thereby
increasing memory access by fourfold
compared to previous MSMC v1.0 25
KeyStone II Memory Subsystem: DDR3
Up to two DDR3 subsystem(s)
per device:
• The first DDR3 subsystem
(DDR3A) supports up to 8 GB
memory addresses and is
connected to the CorePac(s)
through the MSMC.
• When present, the second DDR3
subsystem (DDR3B) supports up
to 2GB memory address and is
connected directly to the
TeraNet.
• Each DDR consists of a 64b/72b
EMIF controller:
– Supports 16-bit, 32-bit, and
64-bit modes .
– Operates at up to 1600 MT/s
– Supports power down of
unused pins when using 16bit or 32-bit width
26
KeyStone II Multicore Navigator
• Consists of the following:
– 2x Queue Manager
– Multiple, dedicated Packet DMA
engines
– 2x infrastructure DMAs
• Provides seamless inter-core
communications (messages and
data exchanges) between cores, IP,
and peripherals. “Fire and forget.”
• Low-overhead processing and
routing of packet traffic to and from
peripherals and cores
• Supports dynamic load optimization
• Data transfer architecture designed
to minimize host interaction while
maximizing memory and bus
efficiency
• Supports up to 16K hardware
queues and 1M descriptors (32K
internal).
27
KeyStone II Network Coprocessor (NETCP)
• Consists of one or two Network
Coprocessor(s)
• Provides hardware accelerators to
perform L2, L3, and L4 processing and
encryption that was previously done in
software
• Packet Accelerator (PA)
– Single IP address option
– UDP (and TCP) checksum and
selected CRCs
– L2/L3/L4 support
– Quality of Service (QoS)
– Multicast to multiple queues
– Timestamps
• Security Accelerator (SA)
– Hardware encryption, decryption,
and authentication
– Supports IPsec ESP, IPsec AH, SRTP,
and 3GPP protocols
• 2x 5-port Ethernet switches (depending
on number of instances of NETCP) with
4-8 ports connecting to 4-8 SGMII ports
and one port connecting to the Packet
and Security Accelerators.
29
KeyStone II External Interfaces
• 8x SGMII ports support
10/100/1000M Ethernet through
1-2x 5-port Ethernet switch(es).
• 2x XGMII ports support up to 10G
Ethernet through a 3-port Ethernet
switch.
• 4x high-bandwidth Serial RapidIO
(SRIO v2.1) lanes for inter-DSP
applications
• 2x PCIe at 5 Gbps
• 2x USB 3.0
• 3x SPI modules with up to four
chip selects per module.
• 2x UART for development/testing
• 3x I2C at 400 Kbps
• 32 GPIO pins
• EMIF 16
• Device-specific interfaces
30
KeyStone II HyperLink Bus
• Provides TI-propriety, high-speed
interconnects termed HyperLink.
• Up to 2x HyperLink modules with 4
lanes each.
• Provides the capability to expand
the device to include hardware
acceleration or other auxiliary
processors
• Supports up to 12.5 Gbaud per lane
31
KeyStone II Miscellaneous Elements
• ARM- and DSP-driven Boot ROM:
– C66x CorePacs support booting from SRIO,
PCIe, I2C Master, I2C Slave, SPI, Ethernet, XIP,
and HyperLink.
– ARM CorePacs support booting from UART,
NAND, XIP, SPI, Ethernet, PCIe, I2C, SRIO and
HyperLink.
– Support varies by peripheral availability
• Semaphore module provides atomic
access to shared chip-level resources.
• Secure Mode (1-time burn security key)
• Power Management:
– Manages power- and clock-switching of
individual IPs and CorePac(s).
– Supports Dynamic Power Switching (DPS):
• Power-state hibernation modes 1 and 2
• Manages each C66x CorePac, each ARM
core, and/or the entire ARM CorePac
– Reset isolation capability on select peripherals
– SmartReflex Class 0 and Class 3
• Up to 5 on-chip PLLs:
–
–
–
–
–
One Main PLL
One PLL for DDR3A
One PLL for DDR3B
One PLL for ARM CorePac
One PLL for Packet Accelerator
• 5x EDMA controllers
• 20x 64-bit timers
• Inter-Processor Communication (IPC)
Registers
32
KeyStone Platform
Device-Specific Offerings
Device-Specific: C6670 for Wireless Apps
Memory Subsystem
64-Bit
DDR3 EMIF
C6670
Coprocessors
2MB
MSM
SRAM
MSMC
RSA
Debug/Trace
RSA
x2
VCP2
Boot ROM
Semaphore
C66x™
CorePac
Power
Management
PLL
TCP3d
EDMA
x2
TCP3e
32KB L1P 32KB L1D
Cache/RAM Cache/RAM
1024KB L2 Cache/RAM
x3
x4
FFTC
x2
BCP
4 Cores @ 1.0 GHz / 1.2 GHz
x3
TeraNet
HyperLink
Switch
Ethernet
Switch
SGMII
x2
x4
SRIO
x6
AIF2
SPI
UART
PCIe
I2C
x2
Multicore Navigator
Queue
Packet
Manager
DMA
GPIO
Device-specific Coprocessors:
• 2x FFT Coprocessor (FFTC)
• Turbo Decoder/Encoder
Coprocessor (TCP3d/3e)
• 4x Viterbi Coprocessor (VCP2)
• Bit-rate Coprocessor (BCP)
• 2x Rake Search Accelerator
(RSA)
Device-specific Interfaces:
• 6x Antenna Interface 2 (AIF2)
Security
Accelerator
Packet
Accelerator
Network Coprocessor
34
Device-Specific: C667x General Purpose
C6671/C6672
C6674/C6678
Memory Subsystem
4MB
MSM
SRAM
MSMC
64-Bit
DDR3 EMIF
Debug/Trace
Boot ROM
Semaphore
C66x™
CorePac
Power
Management
PLL
32KB L1P 32KB L1D
Cache/RAM Cache/RAM
512KB L2 Cache/RAM
x3
EDMA
1 to 8 Cores @ up to 1.25 GHz
x3
TeraNet
HyperLink
Switch
Ethernet
Switch
SGMII
x2
x4
SRIO
x2
TSIP
SPI
UART
x2
PCIe
I2C
GPIO
EMIF 16
Multicore Navigator
Queue
Packet
Manager
DMA
Device-specific Interfaces:
• 2x Telecommunications Serial
Port (TSIP)
• Asynchronous Memory
Interface (EMIF16):
– Connects memory up to
256 MB
– Three modes:
• Synchronized SRAM
• NAND flash
• NOR flash
Security
Accelerator
Packet
Accelerator
Network Coprocessor
35
Device-Specific: C665x General Purpose
C6655/57
Memory Subsystem
1MB
MSM
SRAM
32-Bit
DDR3 EMIF
MSMC
Debug/Trace
Boot ROM
2nd core, C6657 only
Semaphore
C66x™
CorePac
Timers
Security /
Key Manager
Coprocessors
Power
Management
32KB L1P 32KB L1D
Cache/RAM Cache/RAM
PLL
TCP3d
1024KB L2 Cache
x2
VCP2
EDMA
x2
1 or 2 Cores @ up to 1.25 GHz
TeraNet
HyperLink
x4
SRIO
x2
PCIe
McBSP x2
SPI
UART
I2C
UPP
GPIO
EMIF16
x2
Multicore Navigator
Queue
Packet
Manager
DMA
Ethernet
MAC
Device-specific Coprocessors:
• Turbo Decoder Coprocessor
(TCP3d)
• 2x Viterbi Coprocessor (VCP2)
Device-specific Interfaces:
• Asynchronous Memory
Interface (EMIF16)
• Universal Parallel Port (UPP)
• 2x Multichannel Buffered
Serial Ports (McBSP)
Device-specific Memory:
• 1 MB Multicore Shared
Memory (MSM SRAM)
• 32-bit DDR3 Interface
SGMII
36
Device-Specific: C665x Power Optimized
C6654
Memory Subsystem
32-Bit
DDR3 EMIF
Device-specific Interfaces:
• Asynchronous Memory
Interface (EMIF16)
• Universal Parallel Port (UPP)
• 2x Multichannel Buffered
Serial Ports (McBSP)
MSMC
Debug/Trace
Boot ROM
Semaphore
C66x™
CorePac
Timers
Security /
Key Manager
Power
Management
32KB L1P 32KB L1D
Cache/RAM Cache/RAM
x2
Device-specific Memory:
• 32-bit DDR3 Interface
1024KB L2 Cache
EDMA
1 Core @ 850 MHz
TeraNet
x2
PCIe
x2
McBSP
SPI
UART
UPP
GPIO
EMIF16
x2
Multicore Navigator
Queue
Packet
Manager
DMA
I2C
PLL
Ethernet
MAC
SGMII
37
C66x DSP
ARM A15
Max Clock
Ghz
MSMC Shared
Memory – MB
Navigator
Queues
3-Port 10GB
Switch
USB 3.0
HyperLink
SRIO x4
PCIe x2
TSIP
K2E
0x
to
1x
1x
to
4x
ARM = 1.4
DSP = 1.4
2
8K
1x
1x
to
2x
2x
2x
1x
-2x
1x
K2H
4x
to
8x
2x
to
4x
ARM = 1.4
DSP = 1.2
6
16K
2x
1x
-1x
2x
1x
1x
--
5-Port 1GB
Switch
72-bit 1600 MT/s
DDR3 EMIF
Platform
K2H (K2K) Compared to K2E
40
K2H Platform Device Variations
The K2H platform has two variations:
• 66AK2H12
– 8x C66x CorePacs
– Quad-ARM A15 CorePac
– 2x Queue Managers support up to
16K queues
– 1x Network Coprocessor (NETCP)
– 1x USB3.0 to support solid state
drive
– 10GBE interface is NOT available.
43
K2H Platform Device Variations
The K2H platform has two variations:
• 66AK2H12
– 8x C66x CorePacs
– Quad-ARM A15 CorePac
– 2x Queue Managers support up to
16K queues
– 1x Network Coprocessor (NETCP)
– 1x USB3.0 to support solid state
drive
– 10GBE interface is NOT available
• 66AK2H06
– Scaled-down version of 66AK2H12
– 4x C66x CorePacs
– Dual-ARM A15 CorePac
44
K2E Platform Device Variations
The K2E platform has four variations:
• AM5K2E04
– First ARM-only TI multicore device
– Quad-ARM A15 CorePac
– 1x Queue Manager supports up to 8K
queues
– 1x Network Coprocessors (NETCP)
– 1x 3 port 10GBE Switch Subsystem
– Telecommunications Serial Port (TSIP)
– 2x USB 3.0 to support solid state drive
– No SRIO
45
K2E Platform Device Variations
The K2E platform has four variations:
• AM5K2E04
– First ARM-only TI multicore device
– Quad-ARM A15 CorePac
– 1x Queue Manager supports up to 8K
queues
– 1x Network Coprocessors (NETCP)
– 1x 3 port 10GBE Switch Subsystem
– Telecommunications Serial Port (TSIP)
– 2x USB 3.0 to support solid state drive
– No SRIO
• AM5K2E02
–
–
–
–
Scaled-down version of AM5K2E04
Dual-ARM A15 CorePac
1x Network Coprocessor
10GBE not included
46
K2E Platform Device Variations
The K2E platform has four variations:
• AM5K2E04
– First ARM-only TI multicore device
– Quad-ARM A15 CorePac
– 1x Queue Manager supports up to 8K
queues
– 1x Network Coprocessors (NETCP)
– 1x 3 port 10GBE Switch Subsystem
– Telecommunications Serial Port (TSIP)
– 2x USB 3.0 to support solid state drive
– No SRIO
• AM5K2E02
–
–
–
–
Scaled-down version of AM5K2E04
Dual-ARM A15 CorePac
1x Network Coprocessor
10GBE not included
• 66AK2E05
– Same as AM5K2E04 with a single C66x
CorePac added
47
K2E Platform Device Variations
The K2E platform has four variations:
• AM5K2E04
– First ARM-only TI multicore device
– Quad-ARM A15 CorePac
– 1x Queue Manager supports up to 8K
queues
– 1x Network Coprocessors (NETCP)
– 1x 3 port 10GBE Switch Subsystem
– Telecommunications Serial Port (TSIP)
– 2x USB 3.0 to support solid state drive
– No SRIO
• AM5K2E02
–
–
–
–
Scaled-down version of AM5K2E04
Dual-ARM A15 CorePac
1x Network Coprocessor
10GBE not included
• 66AK2E05
– Same as AM5K2E04 with a single C66x
CorePac added
• 66AK2E02
– Same as AM5K2E02 except with a
single-ARM A15 CorePac and a single
C66x CorePac added
48
For More Information
• Device-specific Data Manuals for the KeyStone SoCs
can be found at TI.com/multicore.
• Multicore articles, tools, and software are available
at Embedded Processors Wiki for the KeyStone
Device Architecture.
• View the complete C66x Multicore SOC Online
Training for KeyStone Devices, including details on
the individual modules.
• For questions regarding topics covered in this
training, visit the support forums at the
TI E2E Community website.
50