Transcript Freescale Semiconductor

MPC8360
Micro Controllers
371-1-2403
Introduction
Fall , 2011
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Course Duties
► Attending
all lab sessions is mandatory. (Approvals for not attending a lab
will be given by the instructors only in special cases like reserve duty etc.
► Haganot
– Every 3/4 lab sessions
► Final
report submission.
► Final
exam – must pass with grade greater than 56.
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Grading
Section
%
Final report
15%
Lab execution grade
40%
Final quiz
45%
Passing the final exam (exam grade > 55) is mandatory.
In case of failure, the final course grade will be determined solely based on the
exam.
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Syllabus
Lab Number
Topic
Introduction
MPC8360 Architecture
ADS introduction
CW introduction
Programming model
Registers and Instruction Set
Assembly language
1
Breaking the 32bit Barrier
2
The Load Store Unit
3
Branching and Subroutines
4
Timers
5
Polling & Interrupts
6
DMA
7
Cache memories
8
Final Project
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Freescale Semiconductor
► We
supply the "brains" for all kinds of automotive, consumer,
industrial, networking and wireless applications.
► More
than 20,000 employees in more than 20 countries worldwide,
about 500 employees in Herzelia ISRAEL.
Pioneer
Receivers
Logitech
Harmony remote control
Toshiba
Portable Media Player
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Course Objectives
► Introduction
► Assembly
► Real
to the MPC8360 architecture.
language of the PowerPC microprocessor family.
time embedded coding for the MPC8360.
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The MPC8360 MDS Processor Board
► The
MPC8360EA MDS
Processor Board is an
application development
system that provides a
complete debugging
environment for engineers
developing applications for the
MPC8360 series of Freescale
processors
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PC Connection
To PC USB
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MPC8360
A Simplified Block Diagram
E300
Core
DDR/DDR2
QUICC
Engine™ block
Controller
handles communication tasks with
the outer world.
QUICC Engine
► It supports
a wide range of
Interrupt Controller
communication protocols including
ATM, Ethernet, HDLC, TDM, and
….
POS.
► The E300 Core is the system's "brain"
it executes
► This block
offloads the
communication
instructions
(computer programs) and
managestasks
the from the core
Communication
thereby allowing it to do other
interaction Ports
between all the sub units.
system tasks.
► The core implements a 32-bit the architecture.
► The
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The Core Registers
► General-Purpose
Registers (GPRs)
32 user-level GPRs that are 32 bits wide
r0-r31
► Condition Register (CR)
The CR is a 32-bit user-level register that provides a mechanism for
testing and branching.
The dot (.) suffix enables the update of the CR register
Bits
0
1
2
3
Bits
Description
Description
Less than or
floating-point less than ( LT,FL).
0
Negative (LT)—This1 bit is Greater
set when
theorresult
is negative.
than
floating-point
greater than (GT, FG).
Positive (GT)—This2bit is set
when
the
result
is
positive
Equal or floating-point equal
(EQ,(and
FE). not zero).
Zero (EQ)—This bit3is set Summary
when the overflow
result is or
zero.
floating-point unordered (SO, FU).
Summary overf low (SO)—This
is a copy
of the
f inal statethis
of is
XER[SO]
thefinal state of XER[SO] at the
For integer
compare
instructions,
a copy ofatthe
completion of the instruction
completion of the instruction.
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The Core Registers
► XER
register
32-bit register contains the summary overflow bit, integer carry bit,
overflow bit.
Name
SO
Description
Summary overflow. The summary overflow bit (SO) is set whenever an
instruction (except mtspr) sets the overflow bit (OV). Once set, the SO bit
remains set until it is cleared by an mtspr instruction (specifying the XER) or an
mcrxr instruction. It is not altered by compare instructions, nor by other
instructions (except mtspr to the XER, and mcrxr) that cannot overflow.
Executing an mtspr instruction to the XER, supplying the values zero for SO
and one for OV, causes SO to be cleared and OV to be set.
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The Core Registers
► XER
register
32-bit register contains the summary overflow bit, integer carry bit,
overflow bit.
Name
OV
Description
Overflow. The overflow bit (OV) is set to indicate that an overflow has occurred
during execution of an instruction. Add, subtract from, and negate instructions
having OE = 1 set the OV bit if the carry out of the msb is not equal to the carry
out of the msb + 1, and clear it otherwise. Multiply low and divide instructions
having OE = 1 set the OV bit if the result cannot be represented in 64 bits
(mulld, divd, divdu) or in 32 bits (mullw, divw, divwu), and clear it otherwise.
The OV bit is not altered by compare instructions that cannot
overflow (except mtspr to the XER, and mcrxr).
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The Core Registers
► XER
register
32-bit register contains the summary overflow bit, integer carry bit,
overflow bit.
The following suffixes can be added to a command:
C - records a carry out in CA
E - uses CA as an operand
O - records an overflow in OV and SO
Name
CA
Description
Carry. Set during execution of the following instructions:
• Add carrying, subtract from carrying, add extended, and subtract from
extended instructions set CA if there is a carry out of the msb, and clear it
otherwise.
• Shift right algebraic instructions set CA if any 1 bits have been shifted out of a
negative operand, and clear it otherwise.
The CA bit is not altered by compare instructions, nor by other instructions that
cannot carry (except shift right algebraic, mtspr to the XER, and mcrxr).
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The Core Registers
► Link
register (LR)
The LR can be used to provide the branch target address and to
hold the return address after branch and link instructions. The LR is
32 bits wide.
►Count
register (CTR)
The CTR is decremented and tested automatically as a result of
branch-and-count instructions. The CTR is 32 bits wide.
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MPCxxx Instruction Set
Command
Variations
Instruction
Register (IR)
Functional
Description
Affected
Registers
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MPCxxx Instruction Set
3
4
5
0
0
add r3,r4,r5
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MPCxxx Instruction Set
r0 = 0x00000001
r4 = 0x00001000
addi r4,r0,0x1
r4 = ?0x00000001
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MPCxxx Instruction Set
EXTS (SIMM) = Extends Signed Immediate
r0 = 0x00000001
r4 = 0x00001000
addi r4,r0,0xF000
r4 = ?0xFFFFF000
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MPCxxx Instruction Set
r0 = 0x00000001
r4 = 0x00001000
addi r4,r0,0x1000
addis r4,r4,0x1000
r4 = ?0x10001000
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