Transcript 56F800 Features - Freescale Semiconductor

56F800 Features
Program
Flash
Program
RAM
Boot
Flash
JTAG/OnCE
Data RAM
Voltage
Regulators
Interrupt
Controller
Power
Supervisor
COP
SCI0
SCI1
SPI
MSCAN
GPIOs
Relax. OSC
System Clock
Generator
(OSC & PLL)
External
Memory
Interface
 8K-60K Words Program FLASH, 512 -2K Words
Program RAM
 2K-8K Words Data FLASH, 1K-4K Words Data RAM
 2K Words BootFLASH™
 External Memory Interface
 Voltage regulator
Data Flash
56800
Core
30-40 MIPS
60-80 MHz
 Power Supervisor
6-output
PWM A
 COP Timer
6-output
PWM B
 Up to two 6-Output PWM Modules
2x4 input
ADC
Module B
 CAN Module - 2.0A/B Compliant
 Up to two Quadrature Decoders
Quad Timer
 Up to four 4-Input 12-bit ADCs
Module A,B,C,D  Up to four 16-Bit Quad Timers
Quadrature
Decoder 0
2x4 input
ADC
Module A
 System Clock Gen (some w/ on-chip Relaxation OSC)
Quadrature
Decoder 1
32 – 160 pins
Slide 1
Freescale Semiconductor. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2004
 Event Synchronizer
 Multiple Serial Ports (SCI, SPI)
 Up to 64 General Purpose I/O Pins
 Vectored Interrupt Controller
 JTAG/OnCE™ Debug Port
 32 – 160 LQFP, 160 MBGA Packages
56F820 Features
Program
Flash
Program
RAM
Boot
Flash
JTAG/OnCE
Data RAM
Voltage
Regulators
Interrupt
Controller
Power
Supervisor
COP
SCI0
Data Flash
56800
Core
40 MIPS
80 MHz
 2K Words BootFLASH™
 External Memory Interface
System Clock
Generator
(OSC & PLL)
 System Clock Gen (some w/ on-chip Relaxation OSC)
 Power Supervisor
Quad Timer
Module A
TOD
 COP Timer
 Time Of Day (TOD)
 10-Input 12-bit ADCs
 One 16-Bit Quad Timers
 Event Synchronizer
SSI
SCI2
SPI1
 2K-4K Words Data FLASH, 4K Words Data RAM
 Voltage regulator
SCI1
SPI0
External
Memory
Interface
 31.5K-64K Words Program FLASH, 512 -1K Words
Program RAM
10 input
ADC
Module
GPIOs
100 – 128 pins
Slide 2
Freescale Semiconductor. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2004
 Multiple Serial Ports (SCI, SPI, SSI)
 Up to 64 General Purpose I/O Pins
 Vectored Interrupt Controller
 JTAG/OnCE™ Debug Port
 100 – 128 LQFP Package
56850 Features
Program
RAM
Data RAM
Boot
ROM

120 MIPS at 120 MHz

12K-80K Bytes Program RAM

8K-48K Bytes Data RAM

2K Words Boot ROM

21 External Memory Address lines, 16 data lines and
four programmable chip selects
6 Ch. DMA

Software Programmable Phase Lock Loop
ISSI / ESSI

Six independent channels of DMA

Improved Synchronous Serial Interface (ISSI)

Enhanced Synchronous Serial Interface (ESSI)

Serial Port Interface (SPI)

Serial Communication Interfaces (SCI)

8-bit Parallel Host Interface

Four General Purpose 16-bit Timers

JTAG/Enhanced On-Chip Emulation (EOnCETM) for
unobtrusive, real-time debugging

Computer Operating Properly (COP/Watchdog)

Time of Day

Up to 48 GPIO
External
Memory I/F
SCI
56800E Core
120 MIPS
120 MHz
SPI
8-bit Host I/F
4 Timers
COP
TOD
GPIO
JTAG/EOnCE
81 – 144 Pins
Slide 3
Freescale Semiconductor. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2004
56F8300 Features
Program
Flash
Program
RAM
Boot
Flash
JTAG/EOnCE
Data RAM
Voltage
Regulators
Interrupt
Controller
Power
Supervisor
COP
Temp Sensor
SCI0,1
Data Flash
56800E
Core
60 MIPS
60 MHz
SPI0
FlexCAN (2)
76 GPIOs
System Clock
Generator
(OSC & PLL)
External
Memory
Interface
6-output
PWM A
6-output
PWM B
Quad Timer
Module A,B,C,D
Quadrature
Decoder 0
2x4 input
ADC
Module A
2x4 input
ADC
Module B
Quadrature
Decoder 1
48 - 160 Pins
Slide 4
Freescale Semiconductor. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2004

60MIPS Harvard Architecture Core

32K-512K Bytes Program Flash, 4K Bytes Program RAM

8K-32K Bytes Data Flash, 8K-32K Bytes Data RAM

8K-16K Bytes BootFLASHTM

Code Security Interlock feature for Flash Memory

External Memory Interface with 24 Address lines, 16 data lines
and 8 chip selects

On chip Voltage regulator and ADC reference

System Clock Generator - Dynamically Program System Clock
Frequency

Power Supervisor – Power on Reset and Low Voltage detection.

Computer Operating Properly Timer

Up to two FlexCAN Modules – CAN 2.0 A/B Compliant

Up to two 6-Output PWM Modules

Up to four 4-Input 12-bit ADC

Up to two Quadrature Decoders

Up to four 16-Bit Quad Timer modules – four 16-Bit timers per
module

Multiple Serial Ports – SCIs, SPIs

Up to 76 GPIO

Interrupt Controller – Manages various interrupt request and two
fast interrupts

JTAG/EOnCE™ Debug Port