Transcript ppt

CS-447– Computer Architecture
M,W 10-11:20am
Lecture 4
Instruction Set Architecture
Sep 10th, 2007
Majd F. Sakr
[email protected]
www.qatar.cmu.edu/~msakr/15447-f07/
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Done by now
°Read the first 3 chapters of the book
°Review the slides
°Come see us during office hours
°Working on the project
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Program Concept
°Hardwired systems are inflexible
°General purpose hardware can do
different tasks, given correct control
signals
°Instead of re-wiring, supply a new set
of control signals
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What is a program?
°A sequence of steps
°For each step, an arithmetic or logical
operation is done
°For each operation, a different set of
control signals are needed
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Execution of a Program
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Program -> Sequence of Instructions
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Function of Control Unit
°For each operation a unique code is
provided
• e.g. ADD, MOVE
°A hardware segment accepts the code
and issues the control signals
°We have a computer!
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Computer Components: Top Level View
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Instruction Cycle
°Two steps:
• Fetch
• Execute
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Fetch Cycle
°Program Counter (PC) holds address
of next instruction to fetch
°Processor fetches instruction from
memory location pointed to by PC
°Increment PC (PC = PC + 1)
• Unless told otherwise
°Instruction loaded into Instruction
Register (IR)
°Processor interprets instruction
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Execute Cycle
° Processor-memory
• data transfer between CPU and main memory
° Processor I/O
• Data transfer between CPU and I/O module
° Data processing
• Some arithmetic or logical operation on data
° Control
• Alteration of sequence of operations
• e.g. jump
° Combination of above
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Instruction Set Architecture
Application (MediaPlayer)
The Language of
the Computer
Operating
Compiler
System
Assembler (Windows XP)
Software
Instruction Set Architecture
Hardware
Processor Memory I/O system
Datapath & Control
Layout & Technology
Digital Design
Circuit Design
Transistors
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Chapter objectives
° The goal of this lecture is to discuss an
instruction set (a simple one), showing both
how instructions are represented in hardware
& the relationship between high-level
programming languages (for example Clanguage which you know) and this more
primitive one.
° Next time: the different addressing modes.
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Chapter objectives (2)
° By learning how to represent
instructions, you will also discover the
secret of computing:
the stored-program concept.
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Translating & Starting a Program
C Program
Compiler
Assembly Language Program
Assembler
Object: Machine language module
Linker
Executable: Machine language program
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Translating & Optimizing a Program: The
Compiler
The Compiler transforms the C
program into an assembly language
program, a symbolic form of what the
machine understands.
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Translating a Program: The
Assembler
The Assembler transforms the
Assembly program into a machine
language module.
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Stitching a Program: The
Linker
The linker or link editor takes all the
independently assembled machine language
programs and “stitches” them together.
There are three steps for the linker:
1) Place code and data modules symbolically
in memory
2) Determine the addresses of data and
instruction labels
3) Patch both the internal and external
references
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What Happens in Hardware?
Instructions
CPU
Memory
Data
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Address Bus & Data Bus
Address
Bus
CPU
Memory
Data
Bus
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Address Bus & Data Bus
°Address Bus:
• Names
Address
Bus
• Locations
• Where to go
CPU
Memory
Data
Bus
°Data Bus:
• Content
• Values
• Variables
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Memory Addressing
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Example of Memory with AddrBus = 1
Memory
Memory
0
1
0
1
Decoder
1 to 2
DataBus = 2
DataBus = 1
Address Bus = 1
Decoder
1 to 2
Address Bus = 1
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Example of Memory with AddrBus = 1
Memory
0
1
Decoder
1 to 2
Data Bus = 8
Address Bus = 1
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Example of Memory with AddrBus = 2
Memory
110 0
Decoder
2 to 4
1 01 0
DataBus = 1
Address Bus = 2
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Example of Memory with AddrBus = 2
Memory
110 0
Decoder
2 to 4
1 01 0
DataBus = 2
Address Bus = 2
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Example of Memory with AddrBus = 2
Memory
1 00
1
1
01 0
Decoder
2 to 4
Address Bus = 2
DataBus = 8
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How does the Memory look like?
Location/Address
English Decimal Binary
ML0
ML1
ML2
….
….
ML61
ML62
ML63
0
1
2
….
….
61
62
63
000000
000001
000010
….
….
111101
111110
111111
Content
Decimal
425
212
23
…
…
2047
69
1559
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Binary
00010101001
00011010100
00000010111
…
…
11111111111
00000000101
11000010111
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Memory Addresses Vs Memory Content
As shown in the memory table:
# locations = 64 (ML0 to ML63)
=> memory require 6-bits to address
if the memory word-size = 11-bits
=> largest content in memory is 2048
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In General we Need
#bits
2
= # Memory Locations
If we wish to have 120 locations (120 names),
then 7-bits should be dedicated to address
7
them (2 = 128)
If we first decide to dedicate 6-bits to address the memory
locations, then we will be limited to 64 in their number
6
(2 = 64)
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Instruction Set Design
CPU
Register
File
Memory
Control
Address
Bus
Instructions
Data
Functional
Units
IR
PC
Data
Bus
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What is an instruction set?
° The complete collection of instructions
that are understood by a CPU
° Machine Code
° Binary
° Usually represented by assembly codes
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Elements of an Instruction
° Operation code (Op code)
• Do this operation
° Source Operand reference
• To this to this value
° Result Operand reference
• Put the answer here
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Operation Code (page 342)
° Operation code
(Opcode)
• Do this operation
Name
Mnemonic
Addition
ADD
Subtraction
SUB
…
…
Multiply
MULT
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Processor Operations:
Data
processing
Data
storage
Data
movement
Program flow
control
°Add
°Load
°Read
°GoTo
°Sub
°Store
°Write
°BranchIf
In total, the # of instructions desired is 8,
and these require 3-bits for controlling.
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Registers & How Big?
° CPU must have some working space
(temporary storage)
° Number of Registers varies between
processor designs
° Large enough to hold full address
° Large enough to hold full data word
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How does the Registers File look like?
Name/Address
English Decimal Binary
R0
R1
R2
R3
R4
R5
R6
R7
0
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
Content
Decimal
425
212
23
88
555
2047
69
1559
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Binary
00010101001
00011010100
00000010111
00001011000
01000101011
11111111111
00000100101
11000010111
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Register Address Vs Register Content
As shown in the register file:
# registers = 8 (R0 to R7)
=> registers require 3-bits to address
if the register size = 11-bits
=> largest content in registers is 2047
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In General we Need
2
#bits
= # Registers
If we wish to have 30 registers, then 5-bits
5
should be dedicated to address them (2 = 32)
If we first decide to dedicate 4-bits to address the
registers, then we will be limited to 16 in their number
4
(2 = 16)
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Instruction Design
Data
processing
Data storage
Data
movement
Program flow
control
Sub
000 Load
010 Read
100 GoTo
110
Add
001 Store
011 Write
101 BranchIf
111
I want this operation to make the addition
of two registers & place the result in a third one
Example: Add R1, R2, R3 ; R1 = R2 + R3
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Instruction Design
If in our register file we had 4 registers,
requiring 2-bits for addressing each; thus
the 3 operands desired (R1, R2, R3) in the
Add operation require (2x3 =) 6-bits to be
addressed.
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Instruction Design:
Add R0, R4, R11
Add
R1,
R2,
R3
001
01
10
11
OpCode Destination Source
3-bits
Source
Register
Register Register
2-bits
2-bits
2-bits
9-bits Instruction
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Add R1, R2, R3
Register
File
...
;(= 001011011)
001011011
I.R.
001011011
0
1
2
3
P.C.
2
3
4
What
happens
inside
the
CPU?
Functional
5
6
7
Units
Memory
CPU
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Add R1, R2, R3
R1 011111111
R2 010101010
;(= 001011011)
001010101 R3
...
010101010
Next
001011011
I.R.
Instruction
P.C.
3
4
001010101
+
CPU
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Hypothetical Machine
Consider the following hypothetical machine:
# registers = 16
{R0 to R15}
 require 4-bits to address them (24 = 16)
# memory locations = 256 {M0 to M255}
 require 8-bits to address them (28 = 256)
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Hypothetical Machine (cont’d)
# instructions = 32
{Inst0 to Inst31}
 require 5-bits to be controlled (25 = 32)
where
Inst15 = Add
&
Inst9 = Load
(instruction # 15)
(instruction # 9)
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Example 1:
Add
R0,
R4,
01111 0000 0100
Add R0, R4, R11
R11
; R0 = R4 + R11
1011
And to make it simpler to read and use we will
use the Hex notation
F
0
4
B
And the output of the assembler would simply be
the following machine code: F04B
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The instruction
In fact, each piece of an instruction can be considered
as an individual number, & placing these numbers
side by side forms the instruction.
OpCode Destination Source
Source
Register 1 Register 1 Register 2
5 bits
4 bits
4 bits
4 bits
17-bit Instruction
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Example 2:
Load
Load R13, 127
R13, 127
; R13 = (127)
01001 1101 0111 1111
And in the Hex notation
9
D
7
F
And the output of the assembler would simply be
the following machine code: 9D7F
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The instruction
In fact, the instruction format
Example: OpCode, Operand, Operand, Operand
is fixed only for a specific operation
OpCode
5 bits
Register
4 bits
Memory Address
8 bits
17-bit Instruction
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Note
° When the OpCode consist of a memory R/W, the
operand, Source Register 1 & 2 are combined to
form the address field of the instruction.
° When the OpCode consist of an immediate
instruction, the operand, Source Register 1 & 2
are combined to form the constant whenever that
is required.
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The Instruction
°OpCode: basic operation of the instruction
°Destination Register: register where the
result of the operations will be loaded
°Source Register 1 & 2: registers where the
data will be operated on
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Instruction size = data word size
As you can see from counting the number
of bits, this hypothetical machine
instruction takes exactly 17-bits which
should be the same size as a data word.
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Design by Starting with the Instruction Size
We would like to design a machine with:
•
Instruction size = 8 bits
•
Instruction number = 8
xx x
1. No Operation
2. Add
3. Sub
4. Branch
5. Load
6. Store
7. Increment
8. Decrement
3-bits of the instruction word will be reserved
to control the 8 desired instructions
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Design by Starting with the Instruction Size
So we are left with 5-bits for the operands,
With which we can address at most:
• 32 (= 25) memory locations
• 32 (= 25) registers
But if we chose to do so, we will be
restricted in the number of operands in the
instructions to one
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Design by Starting with the Instruction Size
On the other hand if we wish to have
instructions with 2 explicit operands; that is
still possible with the 5-bits left.
xx x
How ?
!?
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How ? ! ?
xx x
3
4
5
6
7
Using bits 3 with 4 and bits 5 with 6 to address 4
registers.
Bits
Registers addressed # of Registers
3 with 4
5 with 6
R1, R2, R3, R4
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Results
°8 Instructions
°2 operands addressing 4 registers with 2bits each
°1 operand of 5-bits addressing 32 memory
locations
Note: # operands increases
# registers decreases
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Consider this Instruction Set
Data
processing
Data storage
Data
movement
Program flow
control
Sub
000 Load
010 Read
100 GoTo
110
Add
001 Store
011 Write
101 BranchIf
111
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Execution of a simple program
The following program was loaded in memory
starting from memory location 0.
0000 Load R2, ML4
; R2 = (ML4) = 5 = 1012
0001 Read R3, Input14 ; R3 = input device 14 = 7
0010 Sub R1, R3, R2
; R1 = R3 – R2 = 7 – 5 = 2
0011 Store R1, ML5
; store (R1) = 2 in ML5
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The Program in Memory
Load
R2,
ML4
010
10
0100
Read
R3,
Input14
100
11
0100
Sub
R1,
R3,
R2
000
01
11
10
Store
R1,
ML5
011
01
0101
010100110
100110100
000011110
011010111
0
1
2
3
0000
0001
0010
0011
4
0100 000000101
… …
Don’t care
14 1011 Input Port
15 1111 Output Port
Address
Content
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Load R2, ML4
R1
R2 000000101
; 010100110
R3
...
010100110
I.R.
P.C.
0
1
Load
CPU
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; 100110100
Read R3, Input14
R1
R2 000000101
000000111
R3
100110100
010100110
...
1
2
Read
CPU
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Sub R1,
R3,
R1 000000010
R2 000000101
; 000011110
R2
000000111
R3
100110101
000011110
...
000000101
000000111
2
3
Sub
CPU
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; 011010111
Store R1, ML5
R1 Don’t
000000010
Care
R2 000000101
000000111
R3
Next
011010111
Instruction
...
3
4
Store
CPU
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In the Memory
Before
After
Program
Execution
010100110
100110100
000011110
011010111
000000101
0
1
2
3
4
0000
0001
0010
0011
0100
5
0101 Don’t
care
000000010
…
…
14
1011
15
1111
Address
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Don’t care
Input Port
Output Port
Content
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