Transcript Tutorial 11 - IC

CSC2420
Tutorial 11
The Microprocessor and
its Architecture
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Tutorial 11
Objectives
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Revision on lecture note(CPU Architecture)
Intel x86
By Ivan Leung
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Tutorial 11
CPU
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What is CPU?
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one central unit that executes program instructions
communicates with and controls the operation of other
subsystems within the computer
its main function – to fetch and execute instructions
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Tutorial 11
CPU
Floppy
Memory
CPU
Harddisk
Mouse
Monitor
Keyboard
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Tutorial 11
CPU Fundamental
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As you know, fetching and execution are broken down into
smaller steps(e.g. movement between registers, addition by using
ALU, etc…)
Each of these smaller steps is a machine code, i.e. an assembly
instruction
Assembly program will be assembled to machine instructions and
then put in the main memory (You should know that already,
Right?)
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Tutorial 11
CPU Fundamental
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Depends on the machine instruction, the CPU will
generate a set of control signals to control other
subsystem
(You also known that)
CPU bus(What is bus?)
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The bus is internal to the CPU
connected the components in the CPU
(e.g. ALU, GPR, MAR, MDR, PC, …)
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Tutorial 11
CPU
Memory Function Completion:
indicates the operation in
memory is completed
CPU with
Single-bus
CPU internal
bus
CPU bus
Control
MFC Signals READ
From control
unit
....
PC
To main
memory
Address
lines
Memory
bus
ALU
Control
lines
Data
lines
Add
Sub
:
:
XOR
Instruction
Decoder
MAR
MDR
IR
Y
R0
:
:
R(n-1)
ALU
Carry-in
Z
TEMP
Y,Z and TEMP
are registers. That are
transparent to
programmers. CPU will
use it by itself.
From control
unit
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Tutorial 11
Example of Bus organization
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Fetch a Word from MM
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Assume the address of the memory location to be accessed is in R1 and
the memory data are to be loaded into R2
Write a Word to MM
1.
MAR <= [R1]
2.
Read (control to memory)
3.
Wait for MFC from memory
4.
R2 <= [MDR]
CPU idle
1.
MAR <= [R1]
2.
MDR <= [R2], Write signal to control
3.
Wait for MFC from memory
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Tutorial 11
Control signals
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To MM:
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To Registers:
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Read, Write, Reset, etc
Riin – input data to Ri from CPU bus if ‘1’
Riout – output data in Ri to CPU bus if ‘1’;
‘0’: bus is used by others
reset, etc…
To ALU:
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Add, Sub, Mul, Div, etc…
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Tutorial 11
Example of Control Signals
R(i-1) in
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Add data in R1 and R2 registers and
put the result to R3
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R(i-1)
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R(i-1) out
1.
R1out,Yin
2.
R2out, Add, Zin
3.
Zout, R3in
Yin
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Yout
Y

A
Electronic switch:
In control ‘1’ will get
input else will not
Out control ‘1’ will
output the data else ‘0’
will not
B
ALU
Zin
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Z

Zout
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Tutorial 11
1-bit register with Switch
Z means the
tri-state is in
high
impedance
mode
1 bit line of common bus
S
Q
Z/1/0
Control to
SR latch
Q
electronic
switch
R
Zout
Zin
tri-state
Open-collector
(bipolar)
NAND gate
SR latch
(God! What is it?)
Zout
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Tutorial 11
Control Sequence
Execution
Fetch
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ADD A,R1
1.
PCout,MARin,
Read,
Clear Y,
Set carry-in to ALU, Add, Zin
Load [PC] into MAR;
Send Read request to the memory;
Reset Y to all ‘0’s
Load [PC], 0 to ALU inputs, operate PC+1 and write result to Z
2.
Zout,PCin,
WMFC
Load [Z] to PC
wait for memory to complete
3.
MDRout,IRin
Got data in MDR from MM and load it to IR
4.
IRout,MARin,
Read
Load address of A to MAR
Send Read request to the memory
5.
R1out,Yin,
WMFC
Load [R1] to Y and further to ALU
wait for memory to complete
6.
MDRout,Add,Zin
Got data in MDR from MM and load it to ALU, add it to [Y], and write result to
Z
7.
Zout,R1in,End
Load [Z] to R1
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Tutorial 11
Control Sequence
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BRN(conditional/unconditional)
1.
PCout,MARin,
Read,
Clear Y,
Set carry-in to ALU, Add, Zin
Load [PC] into MAR;
Send Read request to the memory;
Reset Y to all ‘0’s
Load [PC], 0 to ALU inputs, operate PC+1 and write result to Z
2.
Zout,PCin,
WMFC
Load [Z] to PC
wait for memory to complete
3.
MDRout,IRin
Got data in MDR from MM and load it to IR
4.
PCout, Yin
Load branch address to Y and further to ALU
5.
IRout, Add, Zin
Load [IR] to ALU and add it to [Y], put the result to Z
6.
Zout,PCin,End
Load [Z] to PC
For step 4, if not satisfy branch condition, then End
branch address = [PC] + Offset
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Tutorial 11
CPU with 3 internal buses
A
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C
required significantly fewer control steps
ADD
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B
Instruction
Decoder
R1,R2,R3 (one clock cycle)
IR
execution phase to be performed in one
clock cycle
Y is not required because ALU can take two
inputs from two registers from two data buses
Z is not required because ALU can write the
result to the destination register by 3rd bus
performs register-to-register operations in
a single clock cycle
PC
Register
File
TEMP
ALU
MDR
MAR
Data
lines
By Ivan Leung
Memory bus
Address
lines
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Tutorial 11
CPU Architecture
Instruction
Unit (IR)
Integer unit
Processor
Instruction
Cache
Floating-point
Processor
Data
Cache
Bus Interface
CPU
System Bus
Main Memory
Input/ Output
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Tutorial 11
Control Signal
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But how to generate the control signals as the control
sequence discussed before?
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By microprogramming
What is microprogramming?

Using a sequence of microinstructions to generates a sequence
of control signals
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Tutorial 11
Microprogramming
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A control word(CW) is a word whose individual bits represent the
various control signals
Each CW represents a set of control signals in one step of control
sequence of an instruction, which is called microinstruction
A sequence of CWs, which is referring to the control sequence of a
machine instruction, is called microroutine
Microprogram memory contains the microroutine of all instructions
Depends on [IR], a starting address of corresponding microroutine is
given to microprogram counter
MicroPC will be incremented and then a sequence of CWs will be given
out
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IR
Starting
address
generator
Clock
 PC
Microprogram
memory
CW
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Tutorial 11
Hand-shaking with Memory
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In the control sequence, there are steps that have to wait for MFC from
memory. A signal WMFC is used.
Read
J
Q
K
Q
MR
To main
memory
Write
MW
J
Q
K
Q
MFC
RUN
Control Setup
Counter
WMFC
Clk
RUN  0 iff
MFC  MR  WAIT
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Tutorial 11
Hand-shaking with Memory

Control
step
Clk
i
i+1
i+2
Why MR?
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if
//
Read
//
//
RUN  WAIT  MFC

But, if it starts at (i+1)-th pulse, RUN  1  1  0  1
However, after the drop of (i+1)-th pulse and
before the raise of (i+2)-th pulse, RUN  1  0  1  0
It is wrong!
MR
//
WMFC
MFC
//
RUN
//
t1
t2
t3
t4
t5
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Tutorial 11
80x86
By Ivan Leung
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Tutorial 11
8086 (Review)
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16-bit processor with 20-bit address bus
Direct mode addressing with memory space of 1MByte
14 words by 16-bit register set
(You should be familiar with them)
Byte addressable
For address and data operands, the least significant byte of the word is stored
in the lower valued address location and the most significant byte in the next
higher address location
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Tutorial 11
8086 (Review)
By Ivan Leung
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Tutorial 11
8086
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Why there is no Program Counter(PC)?
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How stack works?
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How to indicate the next instruction to be executed?
What is the function of SP?
What is the starting position of SP?
How “CALL” works?
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How to jump to other procedure?
How to return(RET) to previous procedure?
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