Transcript Computer Architecture COSC 3330 Summer 2006

Computer Architecture
COSC 3430
Lecture 3: Instructions
1
The Instruction Set Architecture
software
instruction set architecture
hardware
The interface description separating the software and hardware.
Computer’s Internal Clock

Frequency:
 Frequency is number of complete waves passing per unit time.
 It is measured in Hertz (Hz), the number of cycles per second.
 1 KHz = 103 Hz.
 1 MHz = 106 Hz.

Series of electrical pulses with fixed interval between pulses (cycle time)


800 MHZ machine = 800x106 cyc/sec = 1.25x10-9 sec/cyc = 1.25 ns/cyc
Synchronizes all components


Updates state: inputs only change stored values at specific instances
Regulate instruction execution: e.g., 1/clock cycle
cycle time
time for one full cycle
Operations of the Computer Hardware
Chapter 2.2
Assembly Language Instructions

Language of the machine

More primitive than higher level languages
e.g., no sophisticated control flow

Very restrictive
e.g., MIPS arithmetic instructions

We’ll be working with the MIPS instruction set architecture


similar to other architectures developed since the 1980's
used by NEC, Nintendo, Silicon Graphics, Sony, …
Design goals: maximize performance, minimize cost,
reduce design time, minimize memory space (embedded
systems), minimize power consumption (mobile systems)
RISC - Reduced Instruction Set Computer

RISC philosophy




fixed instruction lengths
load-store instruction sets
limited addressing modes
limited operations

MIPS, Sun SPARC, HP PA-RISC, IBM PowerPC, Intel (Compaq)
Alpha, …

Instruction sets are measured by how well compilers use them as
opposed to how well assembly language programmers use them
MIPS Arithmetic Instruction
rd

rs
rt
MIPS assembly language arithmetic statement
add
$t0, $s1, $s2
sub
$t0, $s1, $s2

Each arithmetic instruction performs only one operation

Each arithmetic instruction specifies exactly three operands
destination  source1
op
source2

Those operands are contained in the datapath’s register file
($t0,$s1,$s2)

Operand order is fixed (destination first)
Compiling More Complex Statements

Assuming variable b is stored in register $s1, c is stored in
$s2, and d is stored in $s3 and the result is to be left in $s0,
what is the assembler equivalent to the C statement
h = (b - c) + d
rd
b
c
sub
$t0, $s1, $s2
add
$s0, $t0, $s3
rd
b-c
d
rd
rs
rt
Operands of the Computer Hardware
Chapter 2
section 2.3



MIPS Register File
Operands of arithmetic instructions must be from a limited number
of special locations contained in the datapath’s register file

Register File
Holds thirty-two 32-bit registers
 With two read ports and
 One write port
src1 addr
src2 addr
dst addr
Registers are



write data
5
32 src1
data
5
5
32
locations
32 src2
32
Faster than main memory
Easier for a compiler to use
Can hold variables so that
data
32 bits
 code density improves (since register are named with fewer bits than a memory
location)
Register addresses are indicated by using $
Naming Conventions for Registers
0
$zero constant 0 (Hdware)
16 $s0 callee saves
1
$at reserved for assembler
...
2
$v0 expression evaluation &
23 $s7
3
$v1 function results
24 $t8 temporary (cont’d)
4
$a0 arguments
25 $t9
5
$a1
26 $k0 reserved for OS kernel
6
$a2
27 $k1
7
$a3
28 $gp pointer to global area
8
$t0 temporary: caller saves
29 $sp stack pointer
(callee can clobber)
30 $fp frame pointer
...
15 $t7
(caller can clobber)
31 $ra return address (Hdware)
Registers vs. Memory

Arithmetic instructions operands must be registers,
— only thirty-two registers provided
Processor
Control
Datapath
Devices
Memory
Input
Output

Compiler associates variables with registers

What about programs with lots of variables?
Processor – Memory Interconnections

Memory is viewed as a large, single-dimension array, with an
address

A memory address is an index into the array
read addr/ 32
write addr
Processor
read data 32
Memory
32write data
32 bits
? 232  230 words
locations
MIPS Data Types
Bit: 0, 1
Bit String: sequence of bits of a particular length
4 bits is a nibble
8 bits is a byte
16 bits is a half-word
32 bits (4 bytes) is a word
64 bits is a double-word
Character:
ASCII 7 bit code
Decimal:
digits 0-9 encoded as 0000b thru 1001b
two decimal digits packed per 8 bit byte
Integers: 2's complement
Floating Point
Byte Addresses

Since 8-bit bytes are so useful, most architectures address
individual bytes in memory

Therefore, the memory address of a word must be a multiple
of 4 (alignment restriction)

Big Endian:
leftmost (MSB) byte is word address
IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA

Little Endian:
rightmost (LSB) byte is word address
Intel 80x86, DEC Vax, DEC Alpha (Windows NT)
Addressing Objects: Endianess and Alignment

Big Endian:
leftmost byte is word address

Little Endian:
rightmost byte is word address
little endian byte 0
3
2
1
0
msb
0
big endian byte 0
lsb
1
2
3
0
Aligned
Alignment restriction: requires that
objects fall on address that is multiple
of their size.
Not
Aligned
1
2
3
MIPS Memory Addressing

The memory address is formed by summing the constant
portion of the instruction and the contents of the second (base)
register
$s3 holds 8
Memory
. . . 0001
lw
$t0, 4($s3)
sw
$t0, 8($s3)
...0110
24
...0101
20
...1100
16
...0001
12
...0010
8
...1000
4
...0100
Data
0
Word Address
. . . 0001
#what? is loaded into $t0
#$t0 is stored where?
in location 16
Compiling with Loads and Stores

Assuming variable b is stored in $s2 and that the base address
of array A is in $s3, what is the MIPS assembly code for the C
statement
A[8] = A[2] - b
...
...
A[3]
$s3+12
A[2]
$s3+8
A[1]
$s3+4
A[0]
$s3
lw
$t0, 8($s3)
sub
$t0, $t0, $s2
sw
$t0, 32($s3)
Compiling with a Variable Array Index

Assuming A is an array of 50 elements whose base is in register
$s4, and variables b, c, and i are in $s1, $s2, and $s3,
respectively, what is the MIPS assembly code for the C
statement
c = A[i] - b
add
$t1, $s3, $s3
#array index i is in $s3
add
$t1, $t1, $t1
#temp reg $t1 holds 4*i
add
$t1, $t1, $s4
#addr of A[i]
lw
$t0, 0($t1)
sub
$s2, $t0, $s1
MIPS Instructions, so far
Category
Arithmetic
(R format)
Instr
Op Code
Example
Meaning
add
0 and 32 add $s1, $s2, $s3
$s1 = $s2 + $s3
subtract
0 and 34 sub $s1, $s2, $s3
$s1 = $s2 - $s3
Data
load word
35
lw
$s1, 100($s2)
$s1 = Memory($s2+100)
transfer
store word
43
sw $s1, 100($s2)
Memory($s2+100) = $s1
(I format)
Review: MIPS Organization

Arithmetic instructions – to/from the register file

Load/store instructions - to/from memory
Memory
Processor
1…1100
Register File
src1 addr
src1
data
32
5
src2 addr
32
5
registers
dst addr
($zero - $ra)
src2
5
write data
32 data
32
32 bits
32 ALU
32
read/write
addr
230
words
32
read data
32
write data
32
32
4
0
byte address
(big Endian)
5
1
6
2
32 bits
7
3
0…1100
0…1000
0…0100
0…0000
word address
(binary)
Review: Naming Conventions for Registers
0
$zero constant 0 (Hdware)
16 $s0 callee saves
1
$at reserved for assembler
...
2
$v0 expression evaluation &
23 $s7
3
$v1 function results
24 $t8 temporary (cont’d)
4
$a0 arguments
25 $t9
5
$a1
26 $k0 reserved for OS kernel
6
$a2
27 $k1
7
$a3
28 $gp pointer to global area
8
$t0 temporary: caller saves
29 $sp stack pointer
(callee can clobber)
30 $fp frame pointer
...
15 $t7
(caller can clobber)
31 $ra return address (Hdware)
Review: Unsigned Binary Representation
Hex
Binary
Decimal
0x00000000
0x00000001
0x00000002
0x00000003
0x00000004
0x00000005
0x00000006
0x00000007
0x00000008
0x00000009
0…0000
0…0001
0…0010
0…0011
0…0100
0…0101
0…0110
0…0111
0…1000
0…1001
…
1…1100
1…1101
1…1110
1…1111
0
1
2
3
4
5
6
7
8
9
0xFFFFFFFC
0xFFFFFFFD
0xFFFFFFFE
0xFFFFFFFF
231 230 229
...
23 22 21
20
bit weight
31 30 29
...
3
0
bit position
1 1 1
...
1 1 1 1
bit
1 0 0 0
...
0 0 0 0
-
232 - 1
232 - 4
232 - 3
232 - 2
232 - 1
2
1
1
Review: Signed Binary Representation
-23 =
-(23 - 1) =
1011
and add a 1
1010
complement all the bits
23 - 1 =
2’sc binary
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
decimal
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7