Transcript MIPS I Registers

COM 249 – Computer Organization and
Assembly Language
Chapter 2
Instructions: Language of the Computer
Part I - MIPS
Based on slides from
www-inst.eecs.berkeley.edu/~cs152/
CS 152 L01 Introd uction & MIPS Review ( 2)
Modified by S. J. Fritz 1/2005
UC Regents Fall 2004 © UCB
Introduction
• Words of a computer’s language are
called its instructions
• Its vocabulary is its instruction set.
• Goal:
– Find a language that makes it easy to build
the hardware and the compiler,
– while maximizing performance and
minimizing cost
Review: Instruction Set Design
software
instruction set
hardware
Which is easier to change?
Stored Program Computer
• Basic Principles
– Use of instructions that are
indistinguishable from numbers
– Use of alterable memory for programs
• Demands balance among number of
instructions, the number of clock cycles
needed by an instruction and the speed
of the clock.
Instruction Set Architecture: What Must be Specified?
Instruction
Fetch
Instruction
Decode
Operand
Fetch
Execute
Result
Store
Next
Instruction
° Instruction Format or Encoding
– how is it decoded?
° Location of operands and result
– where other than memory?
– how many explicit operands?
– how are memory operands located?
– which can or cannot be in memory?
° Data type and Size
° Operations
– what are supported
° Successor instruction
– jumps, conditions, branches
- fetch-decode-execute is implicit!
Overview of Design Principles
1. Simplicity favors regularity
– keep all instructions a single size
– require three register operands for arithmetic
– keep register fields in same place in each instruction
2. Smaller is faster
– the reason that MIPS has 32 registers rather than
many more
3.Make the common case fast
– PC-relative addressing for conditional branch
– immediate addressing for constant operands
4.Good design demands good compromises
– compromise between larger addresses and keeping
instructions same length
MIPS I
Instruction set
MIPS
• Typical of instruction sets since 1980’s
• Almost 100 million MIPS processors
manufactured in 2002
• Found in products from Cisco, NEC,
Nintendo, Silicon Graphics, Sony, Texas
Instruments, Toshiba, and others
Historically General Purpose
Registers Dominate
°
1975-1995 all machines use general purpose registers
°
Advantages of registers
• registers are faster than memory
• registers are easier for a compiler to use
-
e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order
vs. stack
• registers can hold variables
- memory traffic is reduced, so program is sped up
(since registers are faster than memory)
- code density improves (since register named with fewer bits
than memory location)
MIPS Architecture
• MIPS – semiconductor company that
built one of the first commercial RISC
architectures
• We will study the MIPS architecture in
some detail in this class Why MIPS
instead of Intel 80x86?
– MIPS is simple, elegant. Don’t want to get
bogged down in gritty details.
– MIPS widely used in embedded apps, x86
little used in embedded, and more embedded
computers than PCs
Instruction Set Architecture
• Early trend was to add more and more instructions
to new CPUs to do elaborate operations
– VAX architecture had an instruction to multiply
polynomials!
• RISC philosophy (Cocke IBM, Patterson,
Hennessy,1980s)–Reduced Instruction Set
Computing
– Keep the instruction set small and simple,
makes it easier to build fast hardware.
– Let software do complicated operations by
composing simpler ones.
Operations of the Computer
Hardware
• The MIPS assembly language instruction
add a, b, c
means a = b+c
• This sequence adds four variables (a=b+c+d+e)
add a, b, c
add a, a, d
add a, a, e
#the sum of b and c is placed in a
#the sum of b,c, and d is now in a
#the sum of b,c,d and e is now in a
• Notice that it takes 3 instructions to add four
variables
MIPS Instructions
• Design Principle 1: Simplicity favors
regularity
• The MIPS assembly language instruction
•
•
•
•
add a, b, c
means a = b+c
Each line represents one instruction
Each instruction has exactly 3 operands for
simplicity
There is one operation per MIPS instruction
Instructions are related to operations (=, +, -, *, /)
in C or Java
Operands of the Computer Hardware
• Operands of arithmetic instructions must be
from a limited number of special memory
locations called registers
• Size of a MIPS register is 32 bits - called a
word
• Major difference between variables in
programming language (unlimited) and
registers is the limited number of registerstypically 32 in MIPS
C, Java Variables vs. Registers
• In C (and most High Level Languages) variables
are declared first and given a type
– Example:
int fahr, celsius;
char a, b, c, d, e;
• Each variable can ONLY represent a value of the
type it was declared as (cannot mix and match int
and char variables).
• In Assembly Language, the registers have no type;
operation determines how register contents are
treated
MIPS I Registers
• Programmable storage
– 232 x bytes of memory
– 31 x 32-bit General Purpose
Registers GPRs (R0 = 0)
r0
r1
°
°
°
r31
PC
lo
hi
0
Operands of the Computer Hardware
• Design Principle 2: Smaller is faster
– Very large number of registers may
increase clock cycle time because it takes
electronic signals longer to travel farther.
– Using more than 32 registers would require
a different instruction format.
– MIPS register convention is to use two
character names following a dollar sign:
$s0, $s1… for variables
$t0, $t1… for temporary locations
$a0, $a1…for arguments
MIPS Addition and Subtraction
• Syntax of Instructions:
1 2,3,4
where:
1) operation by name
2) operand getting result (“destination”)
3) 1st operand for operation (“source1”)
4) 2nd operand for operation (“source2”)
• Syntax is rigid:
– 1 operator, 3 operands
– Why? Keep Hardware simple via regularity
MIPS Addition and Subtraction of
Integers
• Addition in Assembly
– Example: add $s0,$s1,$s2 (in MIPS)
Equivalent to:
a = b + c (in C/Java)
where MIPS registers $s0,$s1,$s2 are
associated with C variables a, b, c
• Subtraction in Assembly
– Example: sub $s3,$s4,$s5 (in MIPS)
Equivalent to:
d = e - f (in C)
where MIPS registers $s3,$s4,$s5 are
associated with C variables d, e, f
Addition and Subtraction
• How would MIPS do this C/Java statement?
a = b + c + d - e;
• Break into multiple instructions
add $t0, $s1, $s2 # temp = b + c
add $t0, $t0, $s3 # temp = temp + d
sub $s0, $t0, $s4 # a = temp - e
• Notice: A single line of C or Java may break
up into several lines of MIPS. Also everything
after the hash mark- # - on each line is
ignored (comments)
Addition and Subtraction
• How do we do this?
f = (g + h) - (i + j);
• Use intermediate temporary register
add $t0,$s1,$s2
add $t1,$s3,$s4
sub $s0,$t0,$t1
# temp0 = g + h
# temp1 = i + j
# f=(g+h)-(i+j)
Constants or Immediate Operands
• Design Principle 3: Make the common case FAST
• Constants occur frequently and by including
constants in arithmetic instructions, they are faster
than if the constants were loaded from memory
• To add 4 to register 3 use add immediate (addi):
addi $s3,$s3,4
# $s3 = $s3+4
Immediates
• Immediates are numerical constants.
• They appear often in code, so there are special
instructions for them.
• Add Immediate:
addi $s0,$s1,10 (in MIPS)
f = g + 10 (in C)
where MIPS registers $s0,$s1 are associated
with C or Java variables f, g
• Syntax similar to add instruction, except that the
last argument is a number instead of a register.
Immediates and Subtraction
• There is no Subtract Immediate in MIPS: Why?
• Limit types of operations that can be done to absolute
minimum
– negative constants are less frequent
– if an operation can be decomposed into a simpler
operation, don’t include it
– addi …, -X = subi …, X => no need for subi
• addi $s0,$s1,-10 (in MIPS)
f = g - 10 (in C)
where MIPS registers $s0,$s1 are associated with
C or Java variables f, g
Register Zero
• One particular immediate, the number
zero (0), appears very often in code.
• So we define register zero ($0 or $zero)
to always have the value 0; for example:
add $s0,$s1,$zero (in MIPS)
f = g (in C)
where MIPS registers $s0,$s1 are associated
with C variables f, g
• Defined in hardware, so an instruction
add $zero,$zero,$s0
will not do anything!
Summarizing...
• In MIPS Assembly Language:
– Registers replace C variables
– One Instruction (simple operation) per line
– Simpler is Better
– Smaller is Faster
• New Instructions:
add, addi, sub
• New Registers:
C or Java Variables: $s0 - $s7
Temporary Variables: $t0 - $t9
Zero: $zero
Memory Operands
• Programming Languages have both
simple variables and complex data
structures.
• How can we handle large data
structures with just a few registers?
– Data structures are kept in memory.
• MIPS includes instructions to transfer
data between memory and registers.
– Data transfer instructions ( load, store)
Memory Operands
• Data transfer Instruction
– load copies data from memory to register
– lw - load word
• Format
opcode register , constant (register)
memory address
• Syntax
lw $t0, 8 ($s3)
offset base address
Memory Addressing
° Since 1980 almost every machine uses addresses to level of 8-bits
(byte)
° 2 questions for design of Instruction Set Architecture:
• Since we could read a 32-bit word as
four loads of bytes from sequential byte addresses
or as one load word from a single byte address,
• How do byte addresses map onto words?
• Can a word be placed on any byte boundary?
Addressing Objects: Alignment
• Since 8-bit bites are useful, most
architectures address individual bites.
• Address of a word matches the address
of one of the four bites in the word
• Addresses of sequential words differ by
4 bytes
• MIPS words must start at addresses
that are multiples of 4 - called alignment
restriction
Addressing Objects: Endianess
• Computers are grouped into those that use:
– the address of the leftmost or “big end byte” as
the word address
– and those that use the “little end” or rightmost
byte
• MIPS is in the BIG Endian group
Addressing Objects: Endianess and Alignment
• Big Endian: address of most significant IBM 360/370,
Motorola 68k, MIPS, Sparc, HP PA
• Little Endian: address of least significant Intel 80x86,
DEC Vax, DEC Alpha (Windows NT)
little endian byte 0
3
2
1
0
msb
lsb
0
0
big endian byte 0
1
2
3
Alignment: require that objects fall
on address that is multiple of their size.
Aligned
Not
Aligned
1
2
3
Addressing arrays
Byte addressing also affects the array index
• The offset to be
added to the base
register ($s3) must
be 4 x 8, or 32
12
8
4
• lw $t0, 32($s3)
0
$s3
Addresses
DATA
Load and Store
•
•
•
•
The complementary instruction to load is store
Store copies data from a register into memory
Format similar to load
MIPS name is sw for store word
– sw $t0, 48($s3) # if $s3 contains the base address
# of A[0] in memory, then this
# stores result into A[12]
Memory and Registers
• Process of putting less commonly used
variables in memory is called spilling the
registers.
• Arithmetic instructions reads two registers,
operates on them and writes the result.
• Data transfer instructions only reads or
writes one operand, without operating on it.
• MIPS register take less time and have
greater throughput than memory, thus a
compiler must use registers efficiently!
Representing Instructions Inside the Computer
• Instructions are stored as a series of bits, or binary
numbers:
000000 100001 10010
opcode
rs
rt
01000
rd
000000
100000
shamt funct
add
17= $s1
18=$s2
8=$t0 no shift
Instruction: add $t0, $s1, $s2
add=32
• There must be a way to represent register names as
numbers
– In MIPS there is a mapping, for example
• $t0… $t7 map to registers 8 …15
• $s0…$s7 map to registers 16…23
MIPS Assembler Register Convention
Name
Number Usage
Preserved across
a call?
the value 0
n/a
return values
no
arguments
no
temporaries
no
saved
yes
temporaries
no
stack pointer
yes
return address
yes
$zero
$v0-$v1
$a0-$a3
$t0-$t7
$s0-$s7
$t18-$t19
$sp
$ra
0
2-3
4-7
8-15
16-23
24-25
29
31
• “caller saved”
• “callee saved”
• On Green Card in Column #2 at bottom
Why Multiple Instruction Formats?
• Design Principle 4: Good design demands good
compromises – there is a need to keep instructions the same
length and desire for a single format
• There is a problem using previous (R-format) when an
instruction needs longer fields
– for example lw must specify two registers and a constant,
but the constant would have only 5 bits available, so the
largest value would be 25 = 32
• Solution: allow I and J formats for different
instructions - but keep all the same length = 32 bits
Instruction Formats
• I-format: used for instructions with
immediates, lw and sw (since the offset
counts as an immediate), and the branches
(beq and bne),
– (but not the shift instructions; later)
• J-format: used for j and jal(jump and
link)
• R-format: used for all other instructions
• It will soon become clear why the instructions
have been partitioned in this way.
Instruction Format Names and Field Descriptions
Instruction Fields
Name
6 bits
(31-26)
5 bits
(25-21)
5 bits
(20-16)
(15-11)
R-format
(6 fields)
op
rs
rt
rd
I-format
(4 fields)
op
rs
rt
J-format
(2 fields)
op
Comments
5 bits
(10-6)
6 bits
(5-0)
All MIPS instructions 32 bits
sham
t
funct
Arithmetic instruction format
Address/immediate
Data Transfer, branch,
immediate instruction format
5 bits
Target address
Jump instruction format
Instruction field notes:
The op and funct fields form the op-code. The rs field gives a source register and rt is also
normally a source register. rd is the destination register, and shamt supplies the shift
amount for logical shift operations.
R-Format Instructions
• Define “fields” of the following number of
bits each: 6 + 5 + 5 + 5 + 5 + 6 = 32
6
5
5
5
5
6
• For simplicity, each field has a name:
opcode
rs
rt
rd
shamt funct
R-Format Instructions
• Meaning of fields:
– rs (Source Register): generally used to specify
register containing first operand
– rt (Target Register): generally used to specify
register containing second operand (note that name
is misleading)
– rd (Destination Register): generally used to specify
register which will receive result of computation
– shamt (Shift amount)
– funct ( Function) - selects specific variant of the
opcode operation - sometimes called function code
R-Format Example
• MIPS Instruction:
add
$8,$9,$10
Decimal number per field representation:
0
9
10
8
0
32
Binary number per field representation:
000000 01001 01010 01000 00000 100000
hex representation:
012A 4020hex
decimal representation:
19,546,144ten
hex
On Green Card: Format in column 1, opcodes in column 3
J-Format Instructions
• Define “fields” of the following number of
bits each:
6 bits
26 bits
• As usual, each field has a name:
opcode
target address
• Key Concepts
– Keep opcode field identical to R-format and
I-format for consistency.
– Combine all other fields to make room for
large target address.
Arrays and Data Structures
• C and Java variables map onto registers; what about
large data structures like arrays?
• 1 of the 5 components of a computer - the memorycontains such data structures
• But MIPS arithmetic instructions only operate on
registers, never directly on memory.
• Data transfer instructions transfer data between
registers and memory:
– Memory to register
– Register to memory
Overview of MIPS
• Simple instructions all 32 bits wide
• Very structured, no unnecessary baggage
• Only three instruction formats
R
op
rs
rt
rd
I
op
rs
rt
16 bit address
J
op
shamt
26 bit address
rely on compiler to achieve performance
— what are the compiler's goals?
• help compiler where we can
funct
Anatomy: 5 components of any Computer
Registers are in the datapath of the
processor; if operands are in memory,
we must transfer them to the processor
to operate on them, and then transfer
back to memory when done.
Personal Computer
Computer
Processor
Control
(“brain”)
Datapath
Registers
Memory
Devices
Input
Store (to)
Load (from)
Output
These are “data transfer” instructions…
Data Transfer: Memory to Registers
• To transfer a word of data, we need to specify
two things:
– Register: specify this by # ($0 - $31) or
symbolic name ($s0,…, $t0, …)
– Memory address: more difficult
• Think of memory as a single onedimensional array, so we can address it
simply by supplying a pointer to a memory
address.
• Other times, we want to be able to offset
from this pointer.
• Remember: “Load FROM memory”
Data Transfer: Memory to Registers
• To specify a memory address to copy
from, specify two things:
– A register containing a pointer to memory
– A numerical offset (in bytes)
• The desired memory address is the sum
of these two values.
• Example:
8($t0)
– specifies the memory address pointed to by
the value in $t0, plus 8 bytes
Data Transfer: Memory to Register
• Load Instruction Syntax:
1 2, 3(4)
– where
1) operation name
2) register that will receive value
3) numerical offset in bytes
4) register containing pointer to memory
• MIPS Instruction Name:
– lw (meaning Load Word, so 32 bits
or one word are loaded at a time)
Data Transfer: Memory to Register
Data flow
Example:lw $t0,12($s0)
This instruction will take the pointer in $s0, add 12
bytes to it, and then load the value from the
memory pointed to by this calculated sum into
register $t0
• Notes:
– $s0 is called the base register
– 12 is called the offset
– offset is generally used in accessing elements of
array or structure: base register points to beginning
of array or structure
Data Transfer: Register to Memory
• Also want to store from register into memory
– Store instruction syntax is identical to Load’s
• MIPS Instruction Name:
sw (meaning Store Word, so 32 bits or one word
are loaded at a time)
Data flow
• Example:sw $t0,12($s0)
This instruction will take the pointer in $s0, add 12
bytes to it, and then store the value from register $t0
into that memory address
• Remember: “ Store INTO memory”
Pointers v. Values
• Key Concept:
• A register can hold any 32-bit value. That
value can be a (signed) int, an unsigned
int, a pointer (memory address), and so on
• If you write add $t2,$t1,$t0
then $t0 and $t1 must contain values
• If you write lw $t2,0($t0)
then $t0 must contain a pointer to
memory
• Don’t mix these up!
Addressing: Byte vs. Word
• Every word in memory has an address, similar to
an index in an array
• Early computers numbered words like C numbers
elements of an array:
– Memory[0], Memory[1], Memory[2], …
Called the “address” of a word
• Computers needed to access 8-bit bytes as well as
words (4 bytes/word)
• Today machines address memory as bytes,
(i.e.,“Byte Addressed”) hence 32-bit (4 byte) word
addresses differ by 4
– Memory[0], Memory[4], Memory[8], …
Compilation with Memory
• What offset in lw to select A[5] in C/Java?
• 4x5=20 to select A[5]: byte v. word
• Compile by hand using registers:
g = h + A[5];
– g: $s1, h: $s2, $s3:base address of A
• 1st transfer from memory to register:
lw $t0,20($s3)
# $t0 gets A[5]
– Add 20 to $s3 to select A[5], put into $t0
• Next add it to h and place in g
add $s1,$s2,$t0 # $s1 = h+A[5]
Translating Assembly Language into
Machine Language
• Suppose $t1 has base of array A and
$s2 corresponds to h in the assignment
A[300] = h + A[300]
• In MIPS : ( try this )
lw $t0, 1200 ($t1)
# temp register $t0 gets A[300]
add $t0, $s2, $t0
# temp register $t0 gets h+ A[300]
sw $t0, 1200($t1)
#stores h = A[300] back into A[300]
MIPS Instruction Encoding
Instruction Format op
rs
rt
rd
shamt funct
add
R
0
reg
reg
reg
0
n.a.
sub
R
0
reg
reg
reg
0
n.a.
addi
I
8
reg
reg n.a.
n.a.
constant
lw
I
35
reg
reg n.a.
n.a.
address
sw
I
43
reg
reg n.a.
n.a.
address
Translating Assembly Language into
Machine Language
lw $t0, 1200 ($t1)
# temp register $t0 gets A[300]
add $t0, $s2, $t0
# temp register $t0 gets h+ A[300]
sw $t0, 1200($t1)
#stores h = A[300] back into A[300]
op
rs
rt
35
9
8
0
18
8
43
9
8
rd
add/shamt funct
1200
8
0
32
1200
Notes about Memory
• Pitfall: Forgetting that sequential word
addresses in machines with byte
addressing do not differ by 1.
– Many an assembly language programmer has
toiled over errors made by assuming that the
address of the next word can be found by
incrementing the address in a register by 1 instead
of by the word size in bytes.
– So remember that for both lw and sw,
the sum of the base address and the
offset must be a multiple of 4
(to be word aligned)
C/Java Decisions: if Statements
• 2 kinds of if statements in C
– if (condition) clause
– if (condition) clause1 else clause2
• Rearrange 2nd if into following:
if
(condition) goto L1;
clause2;
goto L2;
L1: clause1;
L2:
• Not as elegant as if-else, but same
meaning
MIPS Decision Instructions
• Decision instruction in MIPS:
– beq
register1, register2, L1
– beq is “Branch if (registers are) equal”
Same meaning as (using C/Java):
if (register1==register2) goto L1
• Complementary MIPS decision instruction
– bne
register1, register2, L1
– bne is “Branch if (registers are) not equal”
Same meaning as (using C):
if (register1!=register2) goto L1
• Called conditional branches
MIPS Goto Instruction
• In addition to conditional branches, MIPS has an
unconditional branch:
j
label
• Called a Jump Instruction: jump (or branch) directly
to the label without satisfying any condition
• Same meaning as (using C/Java):
goto label
• Technically, it’s the same as:
beq
$0,$0,label
since it always satisfies the condition.
Compiling C/Java if into MIPS
• Compile by hand
if (i == j) f=g+h;
else f=g-h;
• Use this mapping:
f: $s0
g: $s1
h: $s2
i: $s3
j: $s4
(true)
i == j
f=g+h
(false)
i == j?
i != j
f=g-h
Exit
Compiling C/Java if into MIPS
• Compile by hand
if (i == j) f=g+h;
else f=g-h;
(true)
i == j
f=g+h
•Final compiled MIPS code:
beq
sub
j
True: add
Fin:
$s3,$s4,True
$s0,$s1,$s2
Fin
$s0,$s1,$s2
(false)
i == j?
i != j
f=g-h
Exit
#
#
#
#
branch i==j
f=g-h(false)
goto Fin
f=g+h (true)
Note: Compiler automatically creates labels to handle decisions
(branches). Generally not found in HLL code.
“And in Conclusion…”
• Memory is byte-addressable, but lw and sw access
one word at a time.
• A pointer (used by lw and sw) is just a memory
address, so we can add to it or subtract from it
(using offset).
• A Decision allows us to decide what to execute at
run-time rather than compile-time.
• C/Java decisions are made using conditional
statements within if, while, do while, for.
• MIPS Decision making instructions are the
conditional branches: beq and bne.
• New Instructions:
lw, sw, beq, bne, j
Green Card: OPCODES, BASE CONVERSION,
MIPS (1) MIPS
funct
opcode
(5:0)
(31:26)
(2) MIPS
funct (5:0)
ASCII (3)
Binary
Deci Hexa- ASCII
-mal deci-
(1)
sll
add.f
00 0000
0
mal
0
j
srl
mul.f
00 0010
2
2
STX
lui
sync
floor.w.f
00 1111
15
f
SI
NUL
lbu
and
cvt.w.f 10 0100 36
24
$
(1) opcode(31:26) == 0
(2) opcode(31:26) == 17 ten (11 hex );
if fmt(25:21)==16 ten (10 hex ) f = s (single);
if fmt(25:21)==17 ten (11 hex ) f = d (double)
Note: 3-in-1 - Opcodes, base conversion, ASCII!
Green Card
• green card /n./ [after the "IBM
System/360 Reference Data" card]
A summary of an assembly
language, even if the color is not
green. For example,
"I'll go get my green card so I can
check the addressing mode for that
instruction."
Image from Dave's Green Card Collection:
www.jargon.net
http://www.planetmvs.com/greencard/