Transcript Chapter 2, Part I - MIPS Instructions

Chapter 2
Instructions: Language
of the Computer
Part I
Instruction Set (Assembly Lang.)
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Instructions
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Instruction set
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language of the machine
primitive operations that the CPU may execute
commands understood
set of instructions a particular CPU implements
Computer design goal
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easy to build hardware and compiler, maximize
performance, and minimize cost
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Instruction Set
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The repertoire of instructions of a
computer
Different computers have different
instruction sets
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Early computers had very simple
instruction sets
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But with many of the same instruction types
Simplified implementation
Many modern computers also have simple
instruction sets
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Instruction Set Architectures
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Early trend was to add more and more
instructions to new CPUs to do elaborate
operations
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VAX architecture had an instruction to multiply
polynomials!
Reduced Instruction Set Computing (RISC)
philosophy (Cocke IBM, Patterson, Hennessy,
1980s):
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Keep the instruction set small and simple
Makes it easier to build fast hardware.
Let software do complicated operations by composing
simpler ones.
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RISC - Reduced Instruction Set Computer
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RISC philosophy
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fixed instruction lengths
load-store instruction sets
limited addressing modes
limited operations
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MIPS, Sun SPARC, HP PA-RISC, IBM
PowerPC, Intel (Compaq) Alpha, …
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Instruction sets are measured by how well
compilers use them as opposed to how well
assembly language programmers use them
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The MIPS Instruction Set
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MIPS Technologies –
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semiconductor company that built one of the first
commercial RISC architectures
commercialized Stanford MIPS
Used as example throughout textbook
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Typical of many modern ISAs
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See MIPS Reference Data tear-out card, and Appendixes B and E
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MIPS is simple, elegant.
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Large share of embedded core market
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Applications in consumer electronics, network/storage
equipment, cameras, printers, …
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Assembly Instructions
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Each statement (called an instruction), executes
exactly one of a short list of simple commands
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Unlike in C++ (and most other HLLs) where each
line can contain multiple operations
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Instructions are related to operations (=, +, -, *, /)
in C++ or Java
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Ok, enough already…gimme my MIPS!
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MIPS Arithmetic Operations
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Syntax of Instructions:
1
2, 3, 4
where:
1 : operation by name
2 : operand getting result (“destination”)
3 : first operand for operation (“source1”)
4 : second operand for operation
(“source2”)
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MIPS Arithmetic Instructions
“The natural number of operands for an operation like
addition is three…requiring every instruction to have
exactly three operands, no more and no less,
conforms to the philosophy of keeping the hardware
simple”
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three operands and one operation
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Design Principle 1: Simplicity favors regularity
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Regularity makes implementation simpler
Simplicity enables higher performance at lower cost
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Arithmetic Operations
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Addition
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a=b+c
add a, b, c
(in C++)
(in MIPS)
Subtraction
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d=e-f
sub d, e, f
(in C++)
(in MIPS)
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Arithmetic Operations
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How do the following C++ statement?
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a = b + c + d - e;
Compiled into multiple MIPS instructions
add a, b, c
add a, a, d
sub a, a, e
#a=b+c
#a=a+d
#a=a–e
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Notice: A single line of C may become several
lines of MIPS
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Notice: Everything after the hash mark on each
line is ignored (comments)
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Arithmetic Example
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What about this example?
f = (g + h) - (i + j);
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Use temporary variables?
add temp1, g, h
# temp1 = g + h
add temp2, i, j
sub f, temp1, temp2
# temp2 = i + j
# f = temp1 – temp2
# = (g + h) – (i + j)
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Register Operands
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Arithmetic instructions use register operands
ONLY
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Benefit:
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MIPS has 32 registers in the CPU
About half of them are freely available for calculations
Registers are the fastest memory
Access time of < nanosecond (billionth of a sec)
Disadvantage:
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-Registers are the fastest memory
Access time of < nanosecond (billionth of a sec)
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Register Operands
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Drawback: Since registers are in hardware, there
is a predetermined number of them
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Solution: MIPS code must use registers wisely.
32 registers in MIPS
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Design Principle 2: Smaller and faster
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main memory: millions of locations
Each MIPS register is 32 bits wide
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32-bit data called a word in MIPS
Natural unit of access
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Register Operands
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MIPS has a 32 32-bit registers
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Use for frequently accessed data
Numbered 0 to 31
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$0, $1, $2, …, $31
Has assembler names for easier coding
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$8 - $15  $t0, $t1, …, $t9 (temporary values)
$16 - $23  $s0, $s1, …, $s7 (saved variables)
Remaining 16 explained later
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Variables vs. Registers
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C++ variables
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int Farenheit, Celsius;
char a, b, c, d, e;
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Must be declared first with a name & type
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Type must be same throughout program
Registers
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Have no type
Operation determines how register contents
are treated
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Register Operand Examples
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a = b + c;
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Allocations: a:s0, b:$s1, c:$s2
MIPS assembly code:
add $s0, $s1, $s2
a = b + c + d - e;
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Allocations: a, b, c, d, e: $s0, $s1, $s2, $s3, $s4
MIPS assembly code:
add $s0, $s1, $s2
add $s0, $s0, $s3
sub $s0, $s0, $s4
#a=b+c
#a=a+d
#a=a-e
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Register Operand Example
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f = (g + h) - (i + j);
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Allocations:
f:$s0, g:$s1, h:$s2, i:$s3, j:$s4
(g+h):$t0, (i+j):$t1,
MIPS assembly code:
add $t1, $s1, $s2
# temp1 = g + h
add $t2, $s3, $s4
sub $s0, $t1, $t2
# temp2 = i + j
# f = temp1 – temp2
# = (g + h)-(i + j)
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Register Operands
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Arithmetic instructions operands must be
registers,
— only 32 registers provided
Compiler associates variables with registers
What about programs with lots of variables
Control
Input
Memory
Datapath
Processor
Output
I/O
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Memory
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Viewed as a large, singledimension array, with an
address.
A memory address is an
index into the array
"Byte addressing" means
that the index points to a byte
of memory.
“Word addressing”  the
index points to the start of a
word (4 contiguous) bytes.
...
6
8 bits of data
5
8 bits of data
4
8 bits of data
3
8 bits of data
2
8 bits of data
1
8 bits of data
0
8 bits of data
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Memory
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Bytes are nice, but most data items use larger
"words"
For MIPS, a word is 32 bits or 4 bytes.
...
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12
32 bits of data
8
32 bits of data
4
32 bits of data
0
32 bits of data
Registers hold 32 bits of data
232 bytes with byte addresses from 0 to 232-1
230 words with byte addresses 0, 4, 8, ... 232-4
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Memory Alignment
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MIPS requires the address of a word to start at an
address that is a multiple of 4 bytes.
0
Word
Aligned
Not
Aligned
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1
2
3
Last hex digit
of address is:
0, 4, 8, or Chex
1, 5, 9, or Dhex
2, 6, Ahex, or Ehex
3, 7, Bhex, or Fhex
Alignment Restriction: an object can be only be accessed
using an address that is multiple of its size in bytes
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Memory Addressing Pitfall
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Rule: Word addresses are 0,4,8,12,…
Word at address Q is followed by the
word at address Q+4
Pitfall: assuming next word is at Q+1
 Distinction: the next byte is at Q+1
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Registers vs. Memory
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Registers are faster to access than
memory
What if more variables than registers?
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Compiler tries to keep most frequently used
variable in registers (register optimization)
Less frequently used variables in memory:
spilling
Why not keep all variables in memory?
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Smaller is faster:
registers are faster than memory
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