Transcript Lower Power Embedded Architecture Design(1) - VADA

L29:Lower Power Embedded
Architecture Design
성균관대학교 조 준 동 교수, 1999. 8
http://vada.skku.ac.kr
Low Power MPU
Levels for Low Power Design
Hardware-software partitioning,
Power down
Complexity,
Concurrency, Locality,
Algorithm
Regularity, Data representation
Parallelism, Pipelining, Signal correlations
Architecture
Instruction set selection, Data rep.
Circuit/Logic
Sizing, Logic Style, Logic Design
System
Technology
Threshold Reduction, Scaling, Advanced packaging
SOI
Possible Power Savings at Different Design Levels
Level of
Abstraction
Algorithm
Expected Saving
Architecture
10 - 90%
Logic Level
Layout Level
20 - 40%
Device Level
10 - 30%
10 - 100 times
10 - 30%
Present- Day Digital
Systems
• Current systems are complex and heterogenous
Contain many different types of components
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Programmable and Re-configurable processors
Application- specific integrated circuits (ASICs)
Application-specific Instruction processor (ASIP)
Read- Only Memory (ROM) and RAM
I/ O devices and circuitry
• Typically designed from a (large) software
specification
• These heterogenous systems are called
embedded systems
Embedded System Characteristics
• Limited user programmability
– Completely transparent to user, e. g.
automotive engine control
– Limited user interface e. g., intelligent
telephones
– Programmable through application
specific language e.g., postscript printer
• Real- time response No batch
processing
Embedded Systems: Products - 1
Consumer Electronics
HDTV
Computer Related
CD player
personal digital
video game
assistant
video tape recorder
printer
programmable TV
disc drive
camera
music system
multimedia subsystem
graphics subsystem
Communications
cellular phone
graphics terminal
video phone
fax
modems
PBX
Embedded Systems: Products - 2
• Control Systems
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Automotive:engine, ignition, brake system
Manufacturing process control: robotics
Remote control: satellite control, spacecraft control
Other mechanical control: elevator control
• Office Equipment
– smart copier, printer, smart typewriter, calculator
– point- of- sale equipment, credit- card validator,UPC
code reader, cash register
• Medical Applications: instruments( EKG, EEG),
scanning, imaging
Problem Domain Shift
Embedded System Trends I
• Microcomponents grow in importance in IC
industry due to their reusability: DSP, m P, m C
• More embedded systems will require ASICs
– From 20- 70% in 1992 to 60- 70% in 1996
Moral of the story: u-P are joining with highspeed highly-complex ASIC in embedded
systems
Embedded System Trends II
• Embedded systems will require more application
software
– Average moves from 16- 64k lines in 1992 to 64k-512k in
1996
– Requires migration from assembler to C/ C++, implying
requirement for automatic compilation
– From 40- 70% of programmers versus ASIC designers in
1992 to 60- 90% in 1996
Moral of the story: Increase in code- size / code- complexit
is causing a migration to C/ C++ from assembly coding
Embedded Software Optimization
• Code size becomes an important objective
Software will eventually become a part of the chip:
– Need to generate the best possible code
– Can afford longer compilation time
• Need not only traditional optimization techniques,
but also new application- domain-specific
optimizations (e. g., DSP and microcontroller
architectures)
Implementing Digital
Systems
What is an ASIP?
• Application- Specific Instruction Processor
• Processor architecture tailored not just for
application domain (e. g., DSP, microcontrollers),
but for specific sets of applications (e. g., audio,
engine control)
• ASIP characteristics
– Greater design cost (processor + compiler)
– + Higher performance, lower power than commercial
cores, more flexibility than ASIC
ASIP Design
• Given a set of applications, determine m
architecture of ASIP (i. e., configuration of
functional units in datapaths, instruction set)
• To accurately evaluate performance of processor
on a given application need to compile the
application program onto the processor datapath
and simulate object code
• However, the m architecture of the processor is a
design parameter!
Processor Design Flow
Required Compiler Optimizations
• Machine independent optimizations
– Parallelizing transformations (lots of them!) Common
subexpression elimination, Strength reduction, Code motion
• Machine dependent optimizations
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Loop unrolling and software pipelining
Static allocation (non- recursive procedure calls)
Storage layout (arrays, scalars)
Optimization of mode setting instructions
 Instruction selection, scheduling, and register allocation
Common Subexpression
Elimination
Constant Propagation and Folding
Dead Code Elimination
Loop Invariant Code Motion
Array Access Strength Reduction