Transcript MicroBaby Architecture v1

MicroBaby
A simple micro-controller
encompassing all the basics
Start this class by organizing into groups.
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Lecture Overview
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What is MicroBaby
The architecture
Addressing modes
Instructions
Internal registers and control signals
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What is MicroBaby?
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Micro-Baby is a simple computer
architecture, in fact, very simple.
All microcontrollers and microprocessors are
computer architectures, in most cases fairly
simple ones.
In today’s world even microcontrollers are
eons beyond basic.
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Basic assumptions
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It is assumed that the reader possesses a basic
understanding of the binary number system
and the implementation of logic equations in
digital logic using AND, OR, NAND, NOR,
XOR and NOT gates.
It is also assumed that the reader also has a
somewhat beyond basic understanding of
computer architecture.
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Basic styles of architecture
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Micro-Baby is a accumulator based load-store
architecture.
It embodies the essence of the principles of a
RISC architecture.
All instruction execution results are left in the
accumulator.
The accumulator based load-store architecture is
the base processor architecture that all other
architectures build upon
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MicroBaby internal structure
High level and high level internal structure
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CPU
Central Processing Unit
Memory Data Bus
ACC
Control Unit
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Input
Device
Arithmetic/Logic
Unit
Output
Device
ALU
256 bytes
Controller
SR
Accumulator
8
Memory
Loader
On startup
PC
Instr Reg
FF Reset Vector
8
Data Memory
256 bytes
Instruction Memory
256 bytes
Memory Unit
Memory
Address Bus
000000xx
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I/O addresses
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The memory modules
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Interface to the memory modules
Data
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Address
8
r/w
Memory
RAM
ce
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The ALU
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Version 1 of the alu
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mbALU
A
8
8
Mux
B
8
1=B
0 = B’
AddSub
8
Cin
A
Csel
Cout
Cin
Cin’
Add/Sub
Sum
B
Logic
Unit
Csel(1 dt 0)
00 – Cin
01 – NOT Cin
10 – ‘0’
F(3 dt 0)
11 – ‘1’
Lout
8
8
N
AddSub
Arlo
Mux
Z
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All 0’s
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1 = Sum
0 = Lout
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The datapath
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The datapath showing the internal data bus
zero
Mux
amuxtoacc
Accumulator
accout
Cout
N
Z
Mux
bmuxout
DrAcc
BusDr
Aal
Bbu
Ldac
F(3 dt 0)
AddSub
Cin
Arlo
Csel
ALU
alures
Data Bus
Aal
1 = alures
0 = Dbus
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Bbu
1 = zero
0 = Dbus
F function
AND 1000
OR 1110
INV 0011
XOR 0110
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The controller
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Version 2 of the conroller
Controller
SR
Aal
Bbu
Ldacc
Dracc
AddSub
Arlo
Csel
Fixval
PCsel
Program Counter
Instr Reg
F(3 dt 0)
PC
incrementer
PC unit
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Cin
N
Z
Rst
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The instructions
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The instruction
set
Offers the
basics
Would like to
have logical
shift instruction
Maybe rotate
I NSTR
LDA
LDA
STA
ADD
ADD
ADDC
ADDC
SUB
SUB
SUBC
SUBC
INC
DEC
AND
AND
OR
OR
INV
XOR
XOR
CLRA
CLRC
CSET
CMP
CMP
JMP
Op Code
1000 0010
1000 0001
1010 0010
0100 0010
0100 0001
0100 1010
0100 1001
0101 0010
0101 0001
0111 0010
0111 0001
0100 1100
0100 0100
0101 1010
0101 1001
0101 1110
0101 1101
0101 1000
0101 0110
0101 0101
0100 1111
0100 0000
0100 1000
0100 1010
0100 1001
11cn zuuu
2nd by
Addr
Arg
Addr
Addr
Arg
Addr
Arg
Addr
Arg
Addr
Arg
Na
NA
Addr
Arg
Addr
Arg
Na
Addr
Arg
Na
Na
Na
Addr
Arg
Addr
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Addr mode
Direct
Immediate
Direct
Direct
Immediate
Direct
Immediate
Direct
Immeddiate
Direct
Immeddiate
Inherent
Inherent
Direct
Immeddiate
Direct
Immeddiate
Inherent
Direct
Immeddiate
Inherent
Inherent
Inherent
Direct
Immeddiate
Direct
dpcsvec
00000000
01100000
ecsvec/e2csvec
01001 / 01000
00101
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Debugging the controller
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The controller encoding in the microcode
needs debugging to insure correctness.
Note the multiple control signals need to
allow the architecture to function.
Along with discussion of MU0. Groups
should also become familiar with the MU0
architecture.
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Instruction Set Simulator
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An Instruction Set Simulator (ISS) simulates
the operation of a computer architecture
instruction by instruction, updating registers,
memory, and I/O.
A modern ISS has graphical display to show
the contents (values) of registers and possibly
even on busses.
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A Microbaby ISS
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A Microbaby ISS will have a display that
shows the value of the accumulator, the B
input to the ALU, the instruction register, the
temp address register in the controller, and
memory. Both the data memory and the
instruction memory should be displayed.
It should also be possible to show, on a cycle
by cycle basis, the value on the address bus
and the data bus.
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Input and Output
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The Microbaby architecture is a memory
mapped I/O architecture and a few addresses
of data memory will be the I/O ports.
It will be up to each group as to how this I/O
is implemented and what is supported.
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Possibly as part of the graphical display there will
a LED display. With color display to show the
LEDs on/off.
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The software structure
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Graphical Display – Top level and substructure.
Update Graphical Display – update the display items of the
graphical display
Executive – runs the whole ball of wax – should allow for
instruction by instruction, free run, free run with
breakpoints.
Instruction interpreter – disassembles the machine code
into assembly language.
Memory display
I/O display
Define the assembly language specification and implement
an assembler.
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The setup
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Each group will work on their own version of
the system.
IT IS A COMPETITION!! The best product
wins. The best get an A on the assignment.
Others equal to it also get an A.
This is interesting as you set the bar.
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By FRIDAY
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For Friday Jan 22, 2016
Have a plan for your approach to the software
Know the language you are going to use.
Have the assembler language for programmer use
defined.
This will be included in your first progress report, Jan
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BY Jan 29 have the graphical interface running for the
real time simulation display.
Have a good start on the assembler.
Have a good start on the simulation executive.
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Topics for presentation next week
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Next Wednesday Jan 21st
Group 1 – Chapter 1 of text
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Group 2 – Chapter 1 of text
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Processor architecture and organization
Hardware Design Abstraction
MU0 – a simple processor
Processor design tradeoffs
RISC – organization – advantages – drawbacks
Design for low power
Discussion – compare and contrast MU0 to microbaby
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Future topics – for Monday Jan 26
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The Acorn RISC – history of deployment,
more details on company development and
interaction with Apple, VLSI Technology.
This led to Acorn RISC Machines, Ltd. which
became ARM.
Architectural inheritenance from the Berkeley
RISC I and II. Details of the Berkeley RISC
and its history
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Future topics
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The ARM programmer’s model – what the
programmer sees. (2 presentations) - This
includes what is in the datapath and the structure
of memory and I/O seen. Tools for assembler
language programming.
It would be nice to have a “free” simulation tool
for ARM about now. ARM Sim from the
University of Victoria may be the one we use.
Free textbook is available online
Also, wikipedia is a great source for information.
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