Transcript Logical Operations Comparison and Branching

More on the MIPS instruction
set
Basic Instructions
CS-2710
Dr. Mark L. Hornick
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General Instruction categories
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Math
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Addition
Subtraction
Multiply
Divide
Branching
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Conditional
Unconditional
Bit manipulation
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Shift
Set/Unset
Logical Operations
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AND, OR, NOR
Load/Store
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Memory to register
Register to memory
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Four instructions for addition
add rd, rs, rt
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Adds two 32-bit values (in registers rs and rt) together and places the
sum in rd; the values are all interpreted as signed integers and causes
an exception on overflow
addi rs, rt, value
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Adds two 32-bit values rt and value together, placing the sum in rs;
values are treated as signed integers and causes an exception on
overflow
addu rd, rs, rt
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Adds two 32-bit values (in registers rs and rt) together and places the
sum in rd; the values are treated as unsigned integers with no exception
on overflow
addiu rs, rt, value
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Adds two 32-bit values rt and value together, placing the sum in rs;
values are treated as unsigned integers with no exception on overflow
CS-2710
Dr. Mark L. Hornick
3
Only two instructions for
subtraction
sub rd, rs, rt
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Subracts two 32-bit values (in registers rs and rt) together and places
the difference (rs-rt) in rd; the values are all interpreted as signed
integers
subu rd, rs, rt
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Subracts two 32-bit values (in registers rs and rt) together and places
the difference (rs-rt) in rd; the values are all interpreted as unsigned
integers
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There are no *basic* immediate instructions for sub since you can use
addi and addiu with a negative immediate value to have the same
effect:
addi $t0, $t1, -100 # t0 = t1 + (-100) = t1 – 100
addiu $t0, $t1, -100 # t0 = t1 + (-100) = t1 – 100
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This results in a simpler MIPS instruction set
CS-2710
Dr. Mark L. Hornick
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There are no *basic* immediate instructions
for sub since you can use addi and addiu
with a negative immediate value to have the
same effect.
However, you will find that the MARS assembler
still accepts a pseudoinstruction such as
subi $t1, $t2, 100
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# t1 = t2 – 100
A pseudoinstruction is actually a higher-level mechanism to make
MIPS programming easier for humans.
The MIPS assembler deconstructs pseudoinstructions into basic
instructions. MIPS supports many pseudoinstructions.
The above pseudoinstruction becomes two basic instructions
after assembly:
addi $at, $zero, 100
sub $t1, $t2, $at
# at =100
# t1 = t2 – at
Note the use of the $at (assembler temporary) register, which is reserved for use
by the assembler so that it can perform pseudoinstruction breakdowns.
CS-2710
Dr. Mark L. Hornick
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Bit manipulation (1)
sll rd, rt, shamt
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Shift Left Logical: Shifts the bits in rt to the left by shamt bits and puts
the result in rd
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Example: ssl $t0, $t1, 8 # t0 = t1<<8 is equivalent java code
In rd, the MSB bits shifted out are lost; 0’s replace the LSB bits that got shifted left
Thus, if t1=0x12345678, then t0=0x34567800
A quick way to multiply if MSB bits don’t get lost; each shift to the left
doubles the value:
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Let t1 = 0x00000013 (19 decimal)
If t0 = t1<<8, then t0= 0x00001300 ( 4864 = 19*2*2*2*2*2*2*2*2)
srl rd, rt, shamt
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Shift Right Logical: Shifts the bits in rt to the right by shamt bits and puts
the result in rd
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Example: srl $t0, $t1, 8 # t0 = t1>>8 is equivalent java code
In rd, the LSB bits shifted out are lost; 0’s replace the MSB bits that got shifted right
Thus, if t1=0x12345678, then t0=0x00123456
A quick way to divide:
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Let t1 = 0x00001301 (4865 decimal)
If t0 = t1>>8, then t0= 0x00000013
Note loss of precision which is characteristic in integer division as LSB bits are lost!
CS-2710
Dr. Mark L. Hornick
6
Bit manipulation (2)
and rd, rs, rt
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Logical AND: like Java’s rd = rs & rt; does a bit-by-bit logical AND
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Leaves a 1 i-th bit in rd only if the i-th bits of both rs and rt are 1
andi rs, rt, v
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Logical AND: like Java’s rs = rt & v; where v is an immediate value
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V is 0-extended; for instance in andi $t0, $t1, 0x1 , the immediate value 0x1 is zeroextended to be 0x00000001
or rd, rs, rt
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Logical OR: like Java’s rd = rs | rt; does a bit-by-bit logical OR
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Leaves a 1 i-th bit in rd if either or both i-th bits of rs and rt are 1
Leaves a 0 i-th bit in rd only if both i-th bits of rs and rt are 0
ori rs, rt, v
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Logical OR: like Java’s rs = rt | v; where v is an immediate value
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V is 0-extended
nor rd, rs, rt
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Logical NOT: like Java’s rd = !(rs | rt);
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To effectively replicate Java’s rd=!rs write as nor rd, rs, $zero
CS-2710
Dr. Mark L. Hornick
7
Comparison and Branching: instructions
for decision-making
j location_label
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Unconditional jump (goto)
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go to the instruction preceded with the location_label
beq rs, rt, location_label
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Conditional jump (branch) if equal
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If rs==rt, then go to the instruction preceded with the location_label
bne rs, rt, location_label
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If rs!=rt, then go to the instruction preceded with the location_label
bgez rs, location_label
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If rs>=0 then go to the instruction preceded with the location_label
bgtz rs, location_label
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If rs>0, then go to the instruction preceded with the location_label
blez rs, location_label
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If rs<=0 then go to the instruction preceded with the location_label
bltz rs, location_label
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If rs<0, then go to the instruction preceded with the location_label
beqz rs, location_label
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If rs==0 then go to the instruction preceded with the location_label
One of many conditional pseudoinstructions; see the MARS help for others
assembled to
beq rs, $zero, location_label
CS-2710
Dr. Mark L. Hornick
8
If-else-endif in assembly
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Java:
if(i==j)
f=g+h;
else
f=g-h;
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MIPS:
Note: assume i=t0, j=t1, f=t2, g=t3, h=t4
bne
$t0, $t1, else_label
add
$t2, $t3, $t4
j
endif_label
else_label:
sub
$t2, $t3, $t4
endif_label:
# if(i!=j), jump to “else” block
# f = g + h
# jump to end of “if” statement
# f = g - h
# instructions following the “endif” go here…
CS-2710
Dr. Mark L. Hornick
9
Alternate testing for decision making,
based on relative values of registers
slt rd, rs, rt
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Set if Less Than:
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If rs<rt, then rd = 1; otherwise rd = 0
rd can then be checked with beq, beqz, bne, or bnez
slti rt, rs, value
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Set if Less Than Immediate:
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If rs<value, then rt = 1; otherwise rd = 0
sltu rd, rs, rt
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Set if Less Than, Unsigned:
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If rs<rt, then rd = 1; otherwise rd = 0
sltiu rt, rs, value
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Set if Less Than Immediate, Unsigned:
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If rs<value, then rt = 1; otherwise rd = 0
sgt rd, rs, rt
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Set if Greater Than: another pseudoinstruction
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If rs>rt, then rd = 1; otherwise rd = 0
assembled to
slt rd, rt, rs (rs and rt are simply interchanged)
See MARS help for others
CS-2710
Dr. Mark L. Hornick
10
Signed vs. unsigned comparison
slt
sltu
$t0, $s0, $s1
$t1, $s0, $s1
# compare as signed values
# compare as unsigned values
Suppose
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$s0 contains 0xffffffff
$s1 contains 0x00000001
(-1 signed, 2E32-1 unsigned)
(1 either signed or unsigned)
comparing s0 to s1 in a signed manner gives s0<s1 (thus t0=1)
comparing s0 to s1 in an unsigned manner gives s0>s1 (thus t1=0)
CS-2710
Dr. Mark L. Hornick
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Another If-else-endif in assembly
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Java:
If( i>=j) f=g+h; else f=g-h; // assume i=t0, j=t1, f=t2, g=t3, h=t4
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MIPS:
sge $t5, $t0, $t1
# if( i >= j ), set t5=1; otherwise t5=0
beqz $t5, else_label
# if(t5==0) (ie i < j ), jump to “else” block
add $t2, $t3, $t4
#f=g+h
j endif_label
# jump to end of “if” statement
else_label:
sub $t2, $t3, $t4
#f=g-h
endif_label:
# instructions following the “endif” go here…
CS-2710
Dr. Mark L. Hornick
12
Load and Store instructions, revisited
lw rd, n_offset(rs)
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Load Word:
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Loads the word (4 bytes) beginning n_offset bytes from the memory address contained in rs
Ex: lw $t0, 0($t1) #load the 4 bytes beginning at the address contained in t1 into t0
Remember that the most significant byte comes first
sw rd, n_offset(rs)
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Store Word:
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Stores the word (4 bytes) contained in rd to memory beginning n_offset bytes from the memory address
contained in rs
Ex: sw $t0, 4($t1) #store the 4 bytes in memory to beginning 4 bytes above the address contained in t1
(thus if t1 contained 0x00000001, data would be stored at 0x00000005)
Remember that the most significant byte goes first
lw rd, label
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Load from label Address:
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Loads the word (4 bytes) beginning at the address in memory referenced by the label
Ex: lw $t0, x #load the 4 bytes beginning at the address referenced by x into t0; thus if x represents the
memory location 0x10010000, then the value currently stored at that location is loaded into t0
This is one of several pseudoinstructions that are decomposed by the assembler into basic lw (and
othere basic load-related) instructions
la rd, label
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Load label Address:
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Loads the value of the address referenced by the label
Ex: la $t0, x #load the 4 bytes corresponding to the value of x into t0; thus if x represents the memory
location 0x10010000, then the actual value 0x10010000 is loaded into t0.
sw rd, label
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Store at label address:
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Stores the word (4 bytes) contained in rd to memory beginning at the address referenced by the label
Ex: sw $t0, x #store the 4 bytes contained in t0 to memory at the address referenced by x; thus if x
represents the memory location 0x1001000, then the value of t0 is stored at that location.
Note the asymettry!!! This “mirrors” the “lw” instruction, but there is no corresponding “sa” instruction.
CS-2710
Dr. Mark L. Hornick
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