Transcript Some “facts” about software…

Computer Architecture
Undergrad review
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Terminology
• “Digital”
– Discrete, well defined values/steps
– Opposite of analog
– Analogy: digital is to analog as int is to double
• “Binary”
– A system consisting of two states
– on/off, true/false, yes/no, high/low, 0/1
– Basis for modern computers
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Terminology
• “Bit”
– Binary-digit
– Smallest unit of storage in modern computers
• “Nibble” – 4 bits
• “Byte” – 8 bits
• “Word” – typically two bytes but often
refers to the “native” bit length of the
machine
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Data Representation
• 1000001
– one million, one
– sixteen million, seven hundred seventy seven thousand,
two hundred, seventeen
– two hundred sixty two thousand, one hundred forty five
– sixty five
– “A”
– AJMP assembly language instruction
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Boolean Algebra
• Boolean algebra is an algebra that deals
with binary variables and logic operations
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Boolean Algebra
• Boolean algebra consists of…
– A set of symbols that represent variables
• Use letters just like “regular algebra”
• A, B, C, a, b, c…
– Variables are binary (2-valued)
• 0, 1
– Three basic operators
• AND, OR, NOT
– Other symbols
• ()=
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Boolean Operators
• AND
– Notation: A · B, AB, (AB), A(B)
– Yields a value of 1 when both A and B are 1
– Yields a value of 0 when either A or B is 0
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Boolean Operators
• OR
– Notation: A + B
– Yields a value of 1 when either A or B is 1
– Yields a value of 0 when both A and B are 0
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Boolean Operators
• NOT
– Notation: A, A’
– Yields a value of 1 A is 0
– Yields a value of 0 when A is 1
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Boolean Expressions
• As in “regular” algebra, variables,
operators, and symbols can be combined to
form expressions or functions
F(x, a, b) = x + (a · b)
– F is a boolean function of three variables
– Often written as:
F = x + (a · b)
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Boolean Functions
• Typically, we want to exhaustively evaluate
a given boolean function
– That is, we want to know its functional value
for every possible combination of inputs
– This leads us to Truth Tables
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Truth Tables
• List all possible combinations of input values in
the left hand columns
• List expression result in the right hand column
A
B
AB
A
B
A+B
A
A
0
0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
1
1
1
1
1
1
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Axioms
1.
2.
3.
4.
5.
6.
7.
8.
9.
x+0=x
x+1=1
x+x=x
x + x’ = 1
x+y=y+x
x + (y + z) = (x + y) + z
x(y + z) = xy + xz
(x + y)’ = x’y’
(x’)’ = x
10.
11.
12.
13.
14.
15.
16.
17.
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x·1=x
x·0=0
x·x=x
x · x’ = 0
xy = yx
x(yz) = (xy)z
x + yz = (x + y)(x + z)
(xy)’ = x’ + y’
Logic Circuits
• These are the things
computers (and other digital
devices) are made of
• Circuit designers use
Boolean algebra to design
circuits drawn on schematic
drawings
• Fabrication facilities use
schematic drawings to
produce silicon chips
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Schematic Symbols
AND
OR
NOT
More Gates
• NAND
– Shortened form of “not and”
NAND
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More Gates
• NOR
– Shortened form of “not or”
NOR
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NAND/NOR
• So, what’s so special about NAND and
NOR?
• NAND and NOR are considered “universal
gates”
– That is, anything that can be done with
AND/OR/NOT can be done with only NAND
or NOR gates (one or the other, not both)
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NAND/NOR
• The universality of NAND/NOR is important
because it means you can make many copies of a
single gate type on a single piece of silicon and
then use it to create complex circuits on a single
chip
• Exercise
– Show how to make AND, OR, and NOT gates using
only
1. NAND gates
2. NOR gates
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XOR Operator
• Another specialty gate – “odd” function
A
B
A+B
0
0
0
0
1
1
1
0
1
1
1
0
XOR
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K-Maps
• A K-Map is a grid (map) where each square
corresponds to a minterm
BC
A
0
A
00
1
0
0 1
1
01
11
10
0 1 3 2
4 5 7 8
CD
A
B
0
1
AB
0
1
0 1
3 2
00
01
11
10
0 1 3 2
01 4 5 7 8
11 12 13 15 14
10 8 9 11 10
00
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Note the ordering
here is Gray code,
not binary
Sum-of-Products
• This is what we previously called the “sumof-minterms”
• Form the largest power-of-two groupings of
1’s on the K-map
• Create the schematic
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Product-Of-Sums
• Instead of forming large adjacent groups of
1’s (on the K-map), form large adjacent
groups of 0’s
– What does this mean in terms of the original
expression/truth-table?
– It means you have simplified F’, not F
– To “fix” what you’ve done you need only
negate the final result them apply De Morgan’s
theorem
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Example – Sum-of-Products
B’
D’
F
C’
A’
D
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Example – Product-of-Sums
B’
D
F
A’
C’
D’
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So What?
• As it turns out, the sum-of-products can be
easily implemented with NAND gates
• Similarly, the product-of-sums can be easily
implemented with NOR gates
• This may greatly simplify the design thus
saving us money!
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NAND/NOR Implementations
B’
B’
D’
D
C’
A’
A’
C’
D
D’
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Combinational Circuits
• Definition: A connected arrangement of
logic gates with a set of inputs and outputs
• Specifically, they have no memory and no
clock!
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Combinational Circuit Design
• Design a Half-Adder
– A combinational circuit that adds 2 bits
•
•
•
•
Input 1 is call the “Augend”
Input 2 is called the “Addend”
Output 1 is called the “Sum”
Output 2 is called the “Carry”
Augend
Sum
Half-Adder
Addend
Carry
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Combinational Circuit Design
• Design a Full-Adder
– A combinational circuit that adds 3 bits
•
•
•
•
•
Input 1 is call the “Augend”
Input 2 is called the “Addend”
Input 3 is call the “Carry-in”
Output 1 is called the “Sum”
Output 2 is called the “Carry-out”
Carry-in
Augend
Sum
Full-Adder
Addend
Carry-out
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Sequential Circuits
• Two primary differences between
combinational circuits and sequential
circuits
– Sequential circuits are synchronous (use a
clock)
– Sequential circuits have memory (current state)
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Clock
• A series of pulses
– Sometimes referred to as a pulse train
– Basically, it’s an digital signal just oscillates
between 0 and 1
Rising edge
1
0
One period
Falling edge
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Clock
• Clock period is specified in units of time
– Seconds, milliseconds, microseconds…
• Clock frequency is specified in units of
frequency – 1/period – pulses per time-unit
– Hertz, Megahertz, Gigahertz…
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Memory Devices
• Flip flops
– Four basic types
• SR, D, JK, T
– Each type stores 1-bit (two states: 0/1)
– Each maintains its current state until a clock
pulse arrives
• i.e. Ignores input lines until a clock pulse reaches
the clock input
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SR Flip-Flop
• “Set/Reset”
S
– Two input lines
– One clock input line
– Two output lines
Q
C
Q’
R
Characteristic Table
Clock symbol means that
this flip-flop responds to the
rising edge of a clock pulse
• Q(t) refers to the current state
• Q(t+1) refers to the next state
S
R
Q(t+1)
Comments
0
0
Q(t)
No change
0
1
0
Reset to 0
1
0
1
Set to 1
1
1
?
Unspecified
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D Flip-Flop
• “Delay”
D
– One input line
– One clock input line
– Two output lines
Q
C
Q’
Characteristic Table
Clock symbol means that
this flip-flop responds to the
rising edge of a clock pulse
• Q(t+1) refers to the next state
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D
Q(t+1)
Comments
0
0
Clear to 0
1
1
Set to 1
JK Flip-Flop
• “JK”
J
– Two input lines
– One clock input line
– Two output lines
Q
C
Q’
K
Characteristic Table
Clock symbol means that
this flip-flop responds to the
rising edge of a clock pulse
• Q(t) refers to the current state
• Q(t+1) refers to the next state
J
K
Q(t+1)
Comments
0
0
Q(t)
No change
0
1
0
Reset to 0
1
0
1
Set to 1
1
1
Q’(t)
Complement
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T Flip-Flop
• “Toggle”
T
– One input line
– One clock input line
– Two output lines
Q
C
Q’
Characteristic Table
Clock symbol means that
this flip-flop responds to the
rising edge of a clock pulse
• Q(t+1) refers to the next state
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T
Q(t+1)
Comments
0
Q(t)
No change
1
Q’(t)
Complement
Edge-Triggering
• Output of the flip-flop occurs on the edge of
a pulse
– Rising edge (0 to 1 transition)
– Falling edge (1 to 0 transition)
Clock symbol means that
this flip-flop responds to the
rising edge of a clock pulse
Clock symbol means that
this flip-flop responds to the
falling edge of a clock pulse
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Edge-Triggering
Positive (rising) edge-triggered
1
0
positive clock transition
output frozen
Negative (falling) edge-triggered
1
0
negative clock transition
output frozen
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Edge-Triggering
• Setup time
– This is the minimum time that the inputs must remain
constant before the edge transition
• Hold time
– This is the amount of time in which the inputs must not
change after the edge transition
• These values are not to interesting from a
theoretical point of view but can make or break a
circuit in practice
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Master-Slave Flip-Flops
• Two flip-flops of the same type wired together
– Master
• Rising edge triggered
• Receives inputs from “outside world”
• Sends outputs to the slave
– Slave is falling edge triggered
• Falling edge triggered
• Receives inputs from master
• Sends outputs to the “outside world”
• This set-up basically creates a more stable flipflop in terms of set-up and hold times
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Master-Slave JK Flip-Flop
Master
J
Slave
Q
J
C
K
Q
C
Q’
K
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Q’
Sequential Circuits
• Combination of logic gates, flip-flops
(memory elements), and a clock signal
• The circuit can be described in two parts
– The combinational part
– The sequential part
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The Combinational Part
• Describe outputs in terms of logic gates and
flip-flop outputs
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The Sequential Part
• Flip-flop input equations
– Describe the inputs to flip-flop elements in
terms of logic gates and other flip-flop elements
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Designing a Circuit
• The goal of circuit design is to convert a
specification (a bunch of words) into a
circuit
– No different than software development!
• Example
– Design a circuit that counts modulo 4 every
time it receives a 1 on the input line
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State Diagram
X = 0
X = 0
00
X = 1
X = 1
X = 1
01
11
X = 1
X = 0
10
X = 0
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State Table
Present State
Input
Next State
(time t)
(time t+1)
A
B
x
A
B
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
1
0
0
1
0
1
0
1
1
1
1
1
0
1
1
1
1
1
0
0
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Flip-Flop Usage
• We know we need 2 flip-flops since the
counter must count modulo 4 (2 bits)
• We can choose any type we want
– D, T, SR, JK
– By looking at the excitation table for the chosen
type we can create flip-flop equations
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JK Flip-Flop Based Design
State Table Excitation Table
JK Excitation Table
JK flip-flop
Q(t)
Q(t+1)
J
K
0
0
0
x
0
1
1
x
1
0
x
1
1
1
x
0
Present
State
(time t)
Input
Next State
(time t+1)
Flip-Flop Inputs
A
B
x
A
B
JA
KA
JB
KB
0
0
0
0
0
0
x
0
x
0
0
1
0
1
0
x
1
x
0
1
0
0
1
0
x
x
0
0
1
1
1
0
1
x
x
1
1
0
0
1
0
x
0
0
x
1
0
1
1
1
x
0
1
x
1
1
0
1
1
x
0
x
0
1
1
1
0
0
x
1
x
1
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Simplification
• Need to specify combinational circuits for
–
–
–
–
JA input
KA input
JB input
KB input
• Use 3-variable K-maps
– One for each required input/state combination
– Map/simplify the “Flip-Flop Input” columns of the
table
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K-Map Simplification
A
Bx
00
01
11
10
0
0
0
1
0
1
x
x
x
x
A
Bx
00
01
11
10
0
x
x
x
x
1
0
0
1
0
JA
A
Bx
KA
00
01
11
10
0
0
1
x
x
1
0
1
x
x
A
JB
Bx
00
01
11
10
0
x
x
1
0
1
x
x
1
0
KB
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Draw The Logic Gates
x
J
K
J
K
clock
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SET
CLR
SET
CLR
Q
A
Q
Q
Q
B
Integrated Circuit (IC)
• A silicon crystal (chip) containing electronic
components that create the logic gates we’ve been
looking at
–
–
–
–
SSI – Small Scale Integration
MSI – Medium Scale Integration
LSI – Large Scale Integration
VLSI – Very Large Scale Integration
• These refer to the number of logic gates contained
on the chip
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Technologies
•
•
•
•
TTL – Transistor-Transistor Logic
ECL – Emitter-Coupled Logic
MOS – Metal-Oxide Semiconductor
CMOS – Complementary Metal-Oxide
Semiconductor
• These refer to the underlying characteristics
of the process for turning silicon into gates
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Digital Components
•
•
•
•
•
•
•
Decoder
Encoder
Multiplexer
Register
Shift Register
Counter
Memory
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Decoder
• Convert n input bits to a single output bit
B0
B1
B2
Enable
Combinational Logic
– For example: converting binary to octal (3-to-8)
0
1
2
3
4
5
6
7
– What does the circuit look like?
• Start with a truth table
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Encoder
0
1
2
3
4
5
6
7
Enable
Combinational Logic
• Inverse of a decoder
• Convert one input bit to multiple output bits
B0
B1
B2
– For example: converting octal to binary (8-to-3)
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Multiplexer
Inputs
I0
I1
I2
I3
Selectors S0
S1
Combinational Logic
• Routes one of 2n input data lines to a single
output line based on n selection lines
• How many inputs total?
– How big is the truth table?
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Output
Register
• A multi-bit storage element made up of a
group of flip-flops
– Recall flip-flops store 1 bit each
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Register
• CLR is a “clear” input for
asynchronous initialization
• Data can be read out at any
time
• Data is input with the clock
signal, referred to as loading
• Loading can be further
controlled through the use of
additional combinational
circuitry
I0
Clock
SET
CLR
I1
D
SET
CLR
I2
D
SET
CLR
I3
D
SET
CLR
Clear
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D
Q
A0
Q
Q
A1
Q
Q
A2
Q
Q
Q
A3
Shift Register
• Like a “normal” register only bits can be shifted
from one flip-flop to the next
Serial
Input
D
SET
CLR
Q
Q
D
SET
CLR
Q
D
Q
SET
CLR
Clock
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Q
Q
D
SET
CLR
Q
Q
Serial
Output
Counter
• A register that cycles though predetermined
states based on an external input
– Like we just designed using flip-flops
– Parallel load/clear functionality is often added
via combinational circuitry
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Memory
• A group of storage cells and associated
access circuits
• Bits are grouped into words
• Words are the smallest addressable unit
– Typically made up of 1 or more bytes (8-bits)
• Each word in memory is assigned a unique
address
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Memory
Data In
Address
Read
2k word
Memory
n bytes/word
Write
Data Out
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Memory
• How many
address lines?
• How many data
input lines?
• How many data
output lines?
Data In
16
Address
Read
10
1024 word
Memory
2 bytes/word
Write
16
Data Out
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Memory
•
•
•
•
•
K = “Kilo-bytes” = 210 bytes
M = “Mega-bytes” = 220 bytes
G = “Giga-bytes” = 230 bytes
May be specified in either bytes or words
Micro-processors will often talk of “Kilobits” or “Mega-bits”
• Be careful
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Memory
• Two types
– RAM – Random Accessible Memory
• Operations we just looked at
– ROM – Read Only Memory
• Has no input data lines
• Has no write input
• Has no read input (doesn’t need it – just acts when a
valid address is supplied)
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ROM
• Significantly cheaper than RAM since it lacks
versatility
• How does the data get in there?
– Mask programming – data is programmed in at the time
of silicon fabrication
– PROM – special programming devices allow the user to
write data one time
– EPROM – data is erased under ultra-violet light or
electronically, but must be entirely erased and rewritten
(can’t write single words)
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Architectural Functional Block
Diagram
ADDRESS BUS (External) 16 bit
Internal Memory
Internal data bus
Instruction
Reg ister
Ac c
B
Accumulator
I ns truc tion
dec oder/
c ontrol logic
Temporary
register
Temporary
register
PSW
flags
C ontrol Lines
C
AC
F0
RS1
RS2
OV
P
RD/ WR/ PSEN/
ALE/ etc.
ALU
8-bit
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DATA BUS (External) 8 bit
I-RAM
General Registers
STACK
Bit-addressable
SFRs etc.
P. C.
D PTR
Memory Addres s
R egist er
(Us es P0 and P2)
So What?
• A digital computer is a fascinating thing in and of
itself but somewhat useless
• It is the job of the programmer to make it do
something useful
• The programmer’s job is to supply specific,
detailed instructions to move and manipulate
binary data patterns within the architecture to
accomplish a meaningful task
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Sounds Easy
• The problem is that we [the programmers] don’t
want to be burdened with the knowledge of gates,
registers, flip-flops, etc.
• So, we describe the architecture in terms of
various parameters useful to the programmer
• Note that “the programmer” may not be an
“applications programmer” – it may be a
“language compiler writer”, for example
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Descriptive Parameters
• The set of registers within the architecture
– The names and functions (uses) of the registers
• The set of operations available for moving
data between registers and manipulating
data contained within registers
– Microoperations
• The method of specifying the sequence of
execution of the microoperations
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Microoperations
• To describe the operations we use a
language called Register Transfer Language
• We [as programmers] assume that the logic
circuits [combinational and/or sequential]
are available to perform the “transfers”
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Register Transfer Language
• A system for expressing in symbolic form
the microoperation sequences among the
registers of a digital module
– Sound familiar?
• Note that this is not Assembly Language!!!
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Register Transfer Language
(RTL)
• Registers are designated by capital letters
–
–
–
–
–
MAR – Memory Address Register
PC – Program Counter
IR – Instruction Register
Rx – General purpose register
etc.
• Bits within registers are numbered 0 to n-1 (n-bit
register) starting at the LSB (rightmost bit)
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Register Representations
(Pictorial)
R1
7 6 5 4 3 2 1 0
7
0
R1
15
0
15
R2
8 7
R2(H)
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0
R2(L)
Register Transfers
• Move the data from one register to another
R2
R1
• The bit pattern that is in register R1 is copied into
register R2
– Again, we are assured that the circuitry required to
perform the transfer is available
– Implies a parallel load operation
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Conditional Transfer
• Conditionally move the data from one register to
another
if (P = 1) then R2
R1
• The bit pattern that is in register R1 is copied into
register R2 if the control signal P is high (1)
– This isn’t a Java “if/then” statement!
– Again, we are assured that the circuitry required to
perform the transfer is available
– Implies a parallel load operation
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Control Function
• Conditionally move the data from one
register to another
P: R2
R1
• Same meaning as the if/then statement
• P may be a complex logic
expression/combinational circuit
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Parallel Operations
• Some microoperations take multiple clock cycles
(periods)
• Some microoperations can be performed
simultaneously (in parallel)
– During the same clock edge transition
P: R2
R1, R3
R0
– It’s this kind of operation that distinguishes between
computers and “super computers”
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Data Paths
• Lots and lots of little wires
• Every register pair that can transfer data
must be wired together
C3 C2 C1 C0
B3
B2
B1
B0
A3 A2 A1 A0
3
3
2
1
0
3
2
1
0
register C
register B
2
1
0
register A
D3 D2 D1 D0
3
2
1
register D
0
• You would have to do this
for all registers!
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Bus Implementation
bit 3
bit 2
bit 1
bit 0
select 1
select 0
4x1
MUX
3
2
1
D3 C3 B3
4x1
MUX
0
3
2
1
A3
D2 C2 B2
4x1
MUX
0
3
A2
2
1
4x1
MUX
0
3
2
1
D1 C1 B1
A1
D0 C0 B0
0
A0
D3 D2 D1 D0
C3 C2 C1 C0
B3
B2
B1
B0
A3 A2 A1 A0
3
3
3
2
1
0
3
2
1
register D
0
2
1
0
register C
register B
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2
1
register A
0
Three-State Gates
• The most common tri-state gate is the buffer
• What’s a buffer?
input output
• What’s a tri-state buffer?
input
output
control
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0
0
1
1
input
control
output
0
0
open
0
1
0
1
0
open
1
1
1
Register Transfer Language (RTL)
• Arithmetic operations
Addition
R2 R1 + R3
Subtraction
R2 R1 - R3
Increment
R2 R1 + 1
Decrement
R2 R1 - 1
Complement (invert bits)
R2 R1
Negate
R2 R1 + 1
R2 R2 + R1 + 1 Subtraction
• We need circuits to do all these operations
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Logic Microoperations
• Counter-part to the arithmetic
microoperations we looked at last week
• Similar to Boolean functions (expressions)
except that the operands are registers (bit
strings) rather than individual Boolean
variables
– This is exactly what you implemented in code
CSC321
ALU Block Diagram
Stage i
S3
S2
S1
S0
• Combinational circuits that we
looked at previously are inserted
into the boxes
Cin
Arithmetic
Circuit
Stage i
select
Cout
Bi
Ai
Ai-1
Ai+1
0
1
2
3
Logic
Circuit
Stage i
shr
shl
CSC321
4x1
MUX
Fi
Table of Microoperations
Operation Select
Resultant operation/function
S3
S2
S1
S0
Cin
Operation
Function
0
0
0
0
0
F=A
Transfer
0
0
0
0
1
F=A+1
Increment
0
0
0
1
0
F=A+B
Add
0
0
0
1
1
F=A+B+1
Add w/carry
0
0
1
0
0
F=A+B’
Sub w/borrow
0
0
1
0
1
F=A+B’+1
Subtract
0
0
1
1
0
F=A-1
Decrement
0
0
1
1
1
F=A
Transfer
0
1
0
0
x
F=A B
AND
0
1
0
1
x
F=A B
OR
0
1
1
0
x
F=A B
XOR
0
1
1
1
x
F=A’
Complement
1
0
x
x
x
F=shr A
Shift right
1
1
x
x
x
F= shl A
Shift left
CSC321
Making a Computer
•
•
•
•
Binary number system → Boolean functions
Boolean functions → Combinational circuits
Combinational circuits → Sequential circuits
Sequential/Combinational circuits →
Functional units
• Functional units → Computer architecture
CSC321
Defining a Computer
• Computer Architecture
–
–
–
–
–
–
Bus
Registers
Register transfer language
Microoperations
Instruction set
Timing and control
CSC321
Instruction Set
• Instruction (Assembly language statement)
– Binary code
– Consists of an operation code and operand(s)
– Specifies a sequence of microoperations to be executed
• One high level language (e.g. C++/Java) statement specifies a
sequence of instructions
– Stored in memory
– Note that we are talking about a level higher than RTL
but lower than Java, C++, etc.
CSC321
Assembly Language
• Every computer architecture (or family of
architectures) has its own unique assembly
language
• Unlike Java, you should not learn assembly
language syntax, data types, etc.
• You should learn to program/think at the assembly
language level
– It’s a way of thinking that requires intimate knowledge
of the underlying hardware architecture
CSC321
Assembly Language Instructions
• Each instruction has two basic parts
– Operation code (opcode)
• What the instruction wants the processor to do
– Operand(s) (registers, memory addresses)
• Data location that the instruction wants the
processor to manipulated
• Some operands will be explicit while others
will be implicit (implied by the opcode)
CSC321
Assembly Language Instructions
• n-bit instruction format
n-1
m+1
opcode
m
0
operand/address
2(n-1)-(m+1) opcodes
2(m+1) addresses
• Example – 16 bit instruction
15
12 11
opcode
0
operand/address
CSC321
24 = 16 opcodes
212 =4096 addresses
Assembly Language Instructions
• Instructions within the same Assembly
language may be of differing lengths
– i.e. not all instructions utilize the same number
of bits as we saw with the Pentium
CSC321
Internal Operation
• To execute an assembly language instruction the
processor goes through 4 steps
–
–
–
–
Fetch an instruction from memory
Decode the instruction
Read the operands from memory/registers
Execute the instruction
• This is often referred to as the Fetch-Execute cycle
or the Instruction cycle
• To execute a program the processor repeats this
cycle until a halt instruction is reached
CSC321
Internal Operation
• All this is under the control of the Control Unit
• This is the component that decodes the instruction
and sends out microoperations to the rest of the
hardware
– The control unit can be hardwired
• Made up entirely of sequential circuits designed to do precisely
the fetch-execute steps – fixed instruction set
– The control unit can be microprogrammed
• A small programmable processor within the processor –
programmable instruction set
• More on this later
CSC321
Addressing Modes
• In designing a computer architecture the
designer must specify the instruction set
– Opcode/operand pairs
• In specifying operands there are a number
of alternatives
– Immediate instructions
– Direct address operands
– Indirect address operands
CSC321
Addressing Modes
I opcode
address
Mode bit
Immediate
0 addc
Operand
Direct
3
0
0x33
add
Indirect
0x33
0x42
1
0x33
0x33
0x42
0x42
0x88
Operand
Operand
CSC321
add
Registers
• In designing a computer architecture the
designer must specify the register set
• There are essentially two categories
– Special purpose registers
– General purpose registers
CSC321
Special Purpose Registers
• Program Counter (PC)
– Holds the memory address of the next instruction of our
program
• Memory Address Register (AR)
– Holds the address of a location in memory that we want
to access (read/write)
• The size of (number of bits in) these two registers
is determined by the number of memory addresses
in our architecture
CSC321
Special Purpose Registers
• Instruction Register (IR)
– Holds the instruction (opcode/operand) we are about to
execute
• Data Register (DR)
– Holds the operand read from memory to be sent to the
ALU
• Accumulator (AC)
– Holds an input to the ALU and the output from the
ALU
CSC321
Special Purpose Registers
• Input Register (INPR)
– Holds data received from a specified external
device
• Output Register (OUTR)
– Holds data to be sent to a specified external
device
CSC321
General Purpose Registers
• Temporary Register (TR)
– For general usage either by our program or the
architecture
CSC321
Bus
• In designing a computer architecture the designer
must specify the bus layout
– The size of the bus (in bits)
– What is connected to the bus
– Access control to the bus
• Recall that a bus is an efficient alternative to lots
of wires when it comes to transferring data
between registers, control units, and memory
locations
CSC321
Bus Architecture
Memory unit
111
4096x16
ALU
address
AR
001
PC
010
DR
011
AC
100
IR
101
TR
110
E
INPR
OUTR
clock
CSC321
16-bit
Bus
S2 Access
S1
S0 Select
Bus Architecture
• The three access select lines determine which register is
allowed to write to the bus at a given time (recall that only
one write at a time is allowed)
• Registers have load input signals (LD) that tell them to
read from the bus
• If registers are smaller than the bus (less bits) than unused
bits are set to 0
• Some registers have additional input signals
– Increment (INR) and Clear (CLR)
– See figure 5-4, page 130 of the textbook
CSC321
Bus Architecture
• Memory has read/write input signals that tell it
when to take data from the bus and send data to
the bus
• Memory addresses (for both read and write
operations) are always specified via the Address
Register (AR)
– An alternative (used in many architectures) is a two bus
system
• One address bus
• One data bus
CSC321
Bus Architecture
• Results of all ALU (arithmetic, logic, and shift operations)
are always sent to the Accumulator (AC) register
– The ALU is the only way to set values into the accumulator except
for the clear (CLR) and increment (INR) control lines
• Inputs to the ALU come from
– The Accumulator (AC)
– The Data Register (DR)
– The Input Register (INPR)
• The E output from the ALU is the carry-out (Extended AC)
bit
– Many architectures pack this into a register with other status bits
such as overflow
CSC321
Bus Architecture
• Some pairs of microoperations can be
performed in a single clock cycle
– The key is to make sure they don’t both try to put
data on the bus
– Consider the RTL statement
DR ← AC, AC ← DR
– This is allowed since the DR ← AC microoperation
uses the bus while the AC ← DR microoperation
does not
CSC321
Instructions
• Three basic types
– Those that reference memory operands
– Those that reference register operands
– Those that reference I/O devices
• Again, this is only for the fictitious
architecture in the textbook but you will
find similar categorizations in real
architectures
CSC321
Memory Instructions
• There are 14 instructions in this class
– 7 direct memory address forms
– 7 indirect memory address forms
15
I
14
12
11
0
opcode
address
I = 0 means direct memory address
I = 1 means indirect memory address
CSC321
Register Instructions
• There are 12 instructions in this class
– They can use the “operand field” to specify the
register and type of operation since no memory
address is required
15
14
0 1
12
1
1
11
0
Register operation
CSC321
I/O Instructions
• There are 6 instructions in this class
– They can use the “operand field” to specify the
exact operation since no memory address is
required
15
14
1 1
12
1
1
11
0
I/O operation
CSC321
Instruction Decoding
• The control unit evaluates bits 15 – 12 to
determine the instruction format
• At first glance it appears that there can be
only 8 unique instructions since the opcode
resides in 4 bits
• But, additional instructions are created
through the use of the I bit an unused bits in
the operand field
CSC321
Instruction Set Design
• To be useful, an architecture’s instruction
set must contain enough instructions to
allow all possible computations
• Four categories are necessary
–
–
–
–
Arithmetic, logical, shift operations
Moving data to/from memory from/to registers
Control such as branch and conditional checks
Input/output
CSC321
Instruction Set Design
• The set in the book is complete in that all the
possible operations on binary numbers can be
performed through combinations of instructions
• But, the set is very inefficient in that highly used
operations require multiple instructions
• This is why the Pentium instruction set is so large
and complicated – it makes for efficient programs
CSC321
Assembly Language
High Level Language
Instruction
Assembly Language
Instruction
…
Assembly Language
Instruction
…
Assembly Language
Instruction
Machine Code
Instruction
Machine Code
Instruction
Machine Code
Instruction
MicoOp
…
MicorOp
…
MicroOp
MicoOp
MicoOp
…
MicorOp
CSC321
…
MicroOp
…
MicorOp
…
MicroOp
Assembly Language
• Integral part of the computer architecture
• As we saw in previous lectures, the
architecture is designed to perform
assembly language instructions
• Often, the assembly language (or
instruction set) is the first thing defined in
designing a new computer
CSC321