Transcript Some “facts” about software…

Bus Architecture
Memory unit
111
4096x16
ALU
address
AR
001
PC
010
DR
011
AC
100
IR
101
TR
110
E
INPR
OUTR
clock
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16-bit
Bus
S2 Access
S1
S0 Select
Instruction Format
15
I
14
12
11
0
opcode
address
I = 0 means direct memory address
I = 1 means indirect memory address
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The Control Unit
Instruction Register (IR)
15 14 - 12
11 - 0
3x8
Decoder
Other Inputs
12
D7 – D0
I
T15 – T0
4x16
Decoder
Sequence
Counter
Increment
Clear
Master Clock
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Control
Unit
n
Decoding the Instruction
Start
SC <- 0
T0
AR <- PC
T1
IR <- M[AR], PC <- PC + 1
T2
Decode opcode IR(14-12)
AR <- IR(11-0), I<- IR(15)
= 1, register or I/O
• We’ve seen how to fetch
and decode instructions
in RTL notation
• We now need to look at
how to execute each
instruction
= 0, memory reference
D7
= 1, I/O
T3
Execute I/O
Instruction
SC <- 0
I
= 0, register
Execute Register
Instruction
SC <- 0
= 1, indirect
T3
= 0, direct
I
T3
AR <- M[AR]
Execute Memory
Instruction
SC <- 0
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T3
Nothing
Register Instructions
•
•
•
•
•
•
These are all pretty simple
CLA
D7I’T3B11: AC ← 0
CLE
D7I’T3B10: E ← 0
CMA
D7I’T3B9: AC ← AC’
CME
D7I’T3B8: E ← E’
CIR
D7I’T3B7: AC ← shr(AC),
AC(15) ← E, E ← AC(0)
• CIL
D7I’T3B6: AC ← shl(AC),
AC(0) ← E, E ← AC(15)
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Register Instructions
• INC
• SPA
• SNA
• SZA
• SZE
• HLT
D7I’T3B5: AC ← AC + 1
D7I’T3B4: if (AC(15) = 0)
then (PC ← PC + 1)
D7I’T3B3: if (AC(15) = 1)
then (PC ← PC + 1)
D7I’T3B2: if (AC = 0) then (PC ← PC + 1)
D7I’T3B1: if (E = 0) then (PC ← PC + 1)
D7I’T3B0: S ← 0
– S is a flip-flop that starts/stops the master clock
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Register Instructions
• Perhaps the most interesting thing about these
instructions is the condition on which each is selected
– D7I’T3Bi
• The D7I’terms specify the type of operation (register)
• Execution starts at time T3 since no additional
operands need to be fetched from memory
• The Bi term is the interesting one
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Register Instructions
• Note how the opcodes
were assigned hex
(binary) bit patterns
• Notice any patterns?
• Very common practice
in both hardware
design and
programming
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opcodes in hex
opcodes in binary
7800
0111 1000 0000 0000
7400
0111 0100 0000 0000
7200
0111 0010 0000 0000
7100
0111 0001 0000 0000
7080
0111 0000 1000 0000
7040
0111 0000 0100 0000
7020
0111 0000 0010 0000
7010
0111 0000 0001 0000
7008
0111 0000 0000 1000
7004
0111 0000 0000 0100
7002
0111 0000 0000 0010
7001
0111 0000 0000 0001
Memory Instructions
• The condition on which each is selected comes
from the decoding of the operand and starts at
time T4
– DiT4
• The Di term specifies the particular operation
• Execution starts at time T4 assuring the operand
has been fetched from the effective address
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Memory Instructions
• These are a bit more complex
• AND operation
– D0: AC ← AC ^ M[AR]
– This is fine except for the fact that the operation
must take place in the ALU and M[AR] cannot
be routed there directly
– Therefore, we must rework this functional RTL
statement to reflect the actual hardware
architecture
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Logical AND
• We must first get M[AR] into the DR
register
• Then we can perform the AND operation
D0T4: DR ← M[AR]
D0T5: AC ← AC ^ DR, SC ← 0
• Requires two timing phases, T4 and T5
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Arithmetic ADD
• Similar in nature to the AND operation
D1T4: DR ← M[AR]
D1T5: AC ← AC + DR, E ← Cout, SC ← 0
• The result remains in the AC register
• If we want to place it in memory we must
perform a store (STA) instruction
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Load Accumulator
• Similar in nature to the AND operation
D2T4: DR ← M[AR]
D2T5: AC ← DR, SC ← 0
• Recall that the AC is only accessible
through the ALU
• This is why one of the ALU functions was a
transfer (without any arithmetic operation)
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Store Accumulator
• Similar in nature to the AND operation
D3T4: M[AR] ← AC, SC ← 0
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Branch Unconditionally
• A branch is merely a modification of the
program counter (PC) register
D4T4: PC ← AR, SC ← 0
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Branch and Save Return Address
• BSA is the assembly language version of a
subroutine call
• It must store the address of the next instruction
(which is in the PC since we incremented it after
the fetch cycle) somewhere
– It uses the effective address of the operand for this
purpose
• It then performs a branch to the subroutine address
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Branch and Save Return Address
D5T4: M[AR] ← PC, AR ← AR + 1
D5T5: PC ← AR, SC ← 0
• This means that the subroutine actually
starts one memory location after that
specified in the operand
• Consider an example…
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Branch and Save Return Address
After time T5 (when the
instruction is complete)
the PC is here
After time T3 the PC is here
0x20 0 BSA
0x21
0x50
0x50
0x51
0x20 0 BSA
0x21
0x21
0x50
0x51
SUBROUTINE CODE
1 BUN
0x50
SUBROUTINE CODE
0x50
1 BUN
BSA instruction inserts this at time T4
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0x50
Programmer inserts this command
Increment and Skip if Zero
• This is used for creating for loops
• Typically, you will store a negative loop count prior
to using an ISZ command
• It is also used in coordination with a BUN instruction
D6T4: DR ← M[AR]
D6T5: DR ← DR + 1
D6T6: M[AR] ← DR,
if (DR = 0) then (PC ← PC + 1),
SC ← 0
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Increment and Skip if Zero
Calculate loop count into AC
0x20 0 STA
0x21
Store loop count
0xAA
Start of loop
0x50
0x51 0
ISZ
0 BUN
End of loop
0xAA
0x21
-810
0xAA
0xFFFC
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Input/Output Instructions
• Three new flip-flops are introduced into the
architecture to support input/output
commands
– FGI – 1 when information from the input
device is available, 0 otherwise
– FGO – 1 when the output device is ready to
receive information, 0 otherwise
– IEN – interrupt enable
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Input/Output Instructions
• INP
D7IT3B11: AC(0-7) ← INPR, FGI ← 0, SC ← 0
• OUT
D7IT3B10: OUTR ← AC(0-7), FGO ← 0, SC ← 0
• SKI (used in a manner similar to the ISZ)
D7IT3B9: if (FGI = 1) then PC ← PC + 1, SC ← 0
• SKO (used in a manner similar to the ISZ)
D7IT3B8: if (FGO = 1) then PC ← PC + 1, SC ← 0
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Input/Output Instructions
• A problem arises when using the SKI and
SKO instructions
– Their purpose is to set up loop structures
(similar to what we saw with the ISZ
instruction) waiting for an input/output device
to become available
– This could cause large amounts of valuable
time to be wasted
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Now for some more 8050 Assembly
Language Programming
• Subroutines
ACALL sub
…
exit: jmp exit ; don’t let the main program run
; into the subroutine
sub:
…
ret
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What Does ACALL Do?
• Refer to page 17 of the programmer’s guide
a10 a9 a8
1
0
0
0
1
a7 a6 a5 a4 a3 a2 a1 a0
• Operation
(PC) ← (PC) + 2
(SP) ← (SP) + 1
(SP) ← (PC7-0)
(SP) ← (SP) + 1
(SP) ← (PC15-8)
(PC10-0) ← page address
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ACALL
• Note that there is no parameter passage
mechanism
– How can I tell that?
• Therefore, parameters and return values must be
passed in memory or registers
– You need to be careful about this
• Is the memory used outside the subroutine?
• Do the subroutines have to be reentrant?
• etc.
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Programming Assignment
• Previously you wrote code to determine if a
number was prime
• Place that code into a subroutine
• Create a 2nd subroutine that is given a
number in R0 and returns the next larger
prime number in R1
– This subroutine should call the subroutine for
determining if a number is prime
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