Transcript TMA1271 - Introduction to Machine Architecture

TMA1271 - Introduction to Machine
Architecture
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Reference Book:
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Ramesh S. Goankar, “Microprocessor Architecture,
Programming and Applications with 8085”, 5th Edition, Prentice
Hall
Week 1 – Microprocessor Basic Concepts & 8085
Micrprocessor Architecture
Week 2 – Addressing Modes & Classifications of
Instructions of 8085
Week 3 & 4 – Instruction Set of 8085 Microprocessor
Week 5 – Study of 8255 Programmable Peripheral
Interface
TMA1271 - Introduction to Machine
Architecture
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Week 6 – Programming Exercise I
Week 7 – Programming Exercise II
Week 8 – Programming Exercise III
Week 9 – Programming Exercise IV
Week 10 – Programming Exercise V
Week 11 – Programming Exercise VI
Week 12 – Lab Test (Batch A)
Week 13 – Lab Test (Batch B)
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Assessment scheme:
 Programming Exercises – 12% (2%
 Result & Experimentation – 10 marks
 Report – 10 marks
 Total = 20 marks/10 – 2%
 Lab Test – 8 %
 Flowchart – 20 marks
 Program – 40 marks
 Result – 20 marks
 Total = 80 marks/10 – 8%
each)
Organization of A Microprocessor-based
System (Computer)
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CPU – Central Processing Unit
Memory
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I/O
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ROM – Read Only Memory
RAM – Random Access Memory
Keyboard
Display Device
Clock – Square Wave Oscillator (Timing)
System Bus
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Microprocessor (CPU)
 Programmable
integrated device (silicon chip) that
has computing & decision making capabilities
 Communicates & operates in binary numbers 0 & 1,
called bits
 Has a fixed set of instructions in the form of binary
patterns – machine language
 Difficult for humans to remember machine language –
each instruction is represented using abbreviated
names (mnemonics)
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Memory
 Symbolic
representation
Word length
8 bit
FFFF
FFFE
Instruction 1
Instruction 2
Instruction 2
1 word instruction
2 word instruction
64KByte
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0001
0000
address
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Word: no. of bits micro-P recognizes
and processes at a time ( 4 - 64bit ).
Instruction: combination of bit
patterns with specific meaning
known to micro-P.
Program: Set of all instructions.
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I/O
 Microprocessor’s
connection to the outside
world
Input: Keyboard, mouse
 Output: Monitor, printer
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System Bus – wires connecting memory &
I/O to microprocessor
 Address
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Unidirectional
Identifying peripheral or memory location
 Data
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Bus
Bidirectional
Transferring data
 Control
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Bus
Bus
Synchronization signals
Timing signals
Control signal
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Actions performed by microprocessor:
– Memory
 CPU – I/O
 Data Processing
 CPU
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Arithmetic operations
Logical operations
 Control
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Jump
Interrupts
Basic Concepts of Microprocessors
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Differences between:
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Microcomputer – a computer with a microprocessor as its CPU.
Includes memory, I/O etc.
Microprocessor – silicon chip which includes ALU, register
circuits & control circuits
Microcontroller – silicon chip which includes microprocessor,
memory & I/O in a single package.
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Differences between:
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High level language
Assembly language
Machine language
swap (int v[], int k)
{int temp;
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
}
swap;
muli $2, $5,4
add $2, $4,$2
lw $15, 0($2)
lw $16, 4($2)
C compiler
High Level
Languange (in C)
00011100011100
01111000011100
11110000111001
01101011001001
Assembler
Assembly
Languange
Machine
Language
Architecture of Intel 8085 Microprocessor
Intel 8085 Microprocessor
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Microprocessor consists of:
 Control
unit: control microprocessor operations.
 ALU: performs data processing function.
 Registers: provide storage internal to CPU.
 Interrupts
 Internal data bus
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Registers
 General
Purpose Registers
B, C, D, E, H & L (8 bit registers)
 Can be used singly
 Or can be used as 16 bit register pairs
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BC, DE, HL
H & L can be used as a data pointer (holds
memory address)
 Special
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Purpose Registers
Accumulator (8 bit register)
Store 8 bit data
 Store the result of an operation
 Store 8 bit data during I/O transfer
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Flag Register
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8 bit register – shows the status of the microprocessor
before/after an operation
S (sign flag), Z (zero flag), AC (auxillary carry flag), P (parity
flag) & CY (carry flag)
D7
D6
D5
D4
D3
D2
D1
D0
S
Z
X
AC
X
P
X
CY
Sign Flag
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Used for indicating the sign of the data in the accumulator
The sign flag is set if negative (1 – negative)
The sign flag is reset if positive (0 – positive)
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Zero Flag
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Is set if result obtained after an operation is 0
Is set following an increment or decrement operation of that
register
10110011
+ 01001101
--------------1 00000000
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Carry Flag
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Is set if there is a carry or borrow from arithmetic operation
1011 0101
+ 0110 1100
--------------Carry 1 0010 0001
1011 0101
- 1100 1100
--------------Borrow 1 1110 1001
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Auxillary Carry Flag
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Is set if there is a carry out of bit 3
1011 0101
+ 0110 1100
--------------1 0010 0001
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Parity Flag
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Is set if parity is even
Is cleared if parity is odd
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16 – Bit Registers
 Program
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A pointer to the next instruction to be executed
Contains the 16-bit memory address of the next instruction
Updated after processor has fetched the instruction
 Stack
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Counter
Pointer
Stack – an area in memory in which temporary info is stored
Stack – FILO (First In Last Out) basis
Holds the address of the top of the stack
Non Programmable Registers
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Instruction Register & Decoder
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Instruction is stored in IR after fetched by processor
Decoder decodes instruction in IR
Internal Clock generator
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3.125 MHz internally
6.25 MHz externally
Basic Working of a Microprocessor
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Instructions are stored
sequentially in memory
Microprocessor
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Fetches instruction from
memory
Decodes instruction
Executes instruction
Interrupts of 8085 Microprocessor
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Maskable Interrupts
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Microprocessor can ignore or delay interrupt request
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INTR – General purpose interrupt
RST 5.5, RST 6.5, RST 7.5 – Restart interrupts, higher priorities
Nonmaskable Interrupts
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Enabled by default
Cannot be disabled
Microprocessor must respond to it immediately
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TRAP – highest priority
Grouping of Signals of 8085 Microprocessor
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Power supply and frequency signals
Address bus signals
Data bus signals
Control and status signals
Externally initiated signals & external signal
acknowledgement
Serial I/O port signals
Address bus signals, Data bus signals
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AD0-AD7, A8-A15
 16 address lines – 2 sets
 Most significant bits (A8-A15) – single directional
 Least significant bits (AD0-AD7) – bidirectional
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Multiplexed with the bits of bi-directional data bus
It is used as both address and data bus
Control and status signals
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Status_ lines:
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IO/M
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Differentiate I/O and memory applications
High – I/O
Low – Memory
S1, S0 – status signals, to indicate the type of machine cycle in
progress
Control
lines: __
_
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RD, WR & INTA
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RD – data on the data bus to be read into processor
WR – data on the data bus to be written to processor
INTA – acknowledge an INTR interrupt
Externally initiated signals & signal
acknowledgement
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Initiated signals
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Reset In – reset CPU
Hold – suspend CPU operation
Ready – CPU go into wait state, to sync with slower devices
Signal acknowledgement
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Reset out – high once CPU is rest
HLDA – acknowledges hold signal