Demonstration of STDP based Neural Networks on an

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Transcript Demonstration of STDP based Neural Networks on an

DEMONSTRATION OF STDP BASED
NEURAL NETWORKS ON AN FPGA
Kuldeep Singh
OVERVIEW

Aim and Motivation

Problem Statement

Background

Related work

Plan of action
AIM


To develop a prototype for demonstrating the
feasibility of STDP based neural networks before
chip level implementation.
To provide configurability to quickly test the
effectiveness of STDP
MOTIVATION

Actual chip level design a lengthy and expensive
process.

Simulations in software are very slow.

Different applications require redesigning of chip
PROBLEM


Implementation of neurons, synapses and interconnects on the FPGA.
Provision for modification of parameters
Need to alter initial weights of the synapses
 Specification of configuration
 Network topology


Minimization of FPGA resources usage
STDP BASED LEARNING
Synaptic weights are modified according to time
of the spike at the pre-synaptic input.
 Synapses helping to spike are strengthened(LTP)
 Noncontributing synapses are weakened(LTD)

STDP (CONTINUED…)

STDP algorithm
P(t) = exp(−t / τp ) and Q(t) = exp(−t / τq )
RELATED WORK

Design of analog/digital simulator
dedicated to real-time neurocomputing
(B. Belhadj et al.)
FUNCTION OF DIGITAL HARDWARE
Get neurons config. parameters from the user
send them to the ASICs.
 Map the neural network topology
 Give to user the neural state information
 Receive spike events, send the synaptic signals to
post-synaptic neurons
 Compute STDP and update synaptic weights

DISTRIBUTION OF COMPUTATIONAL TASKS
IN THE SYSTEM
FINAL IMPLEMENTATION

25 neurons in network

126 slices used for implementing STDP

Exponential block is shared in a TDMA manner
ANALYSIS

Pros

Neurons implemented in ASIC
High density is achieved
 Better replication of neural dynamics



Lower power consumption
Cons
Inflexibility
 Longer design time
 Susceptibility to noise

Thermal noise
 Power supply variation
 Device variation

PLAN


Implementation of the neurons, synapses and
inter-connects on the FPGA.
Provision for the user to modify the parameters.


GUI for the user to modify the initial parameters and
topology
Testing of the final implementation for various
testcases.
IMPLEMENTATION OF STDP

Pre-calculate the synaptic weight changes.

Implement the full algorithm
IMPLEMENTATION OF A NEURON


One possibility is to use Snider’s neuron model
Start with the basics and mimic the behavior of
neuron.
THANK YOU
Questions? Comments? Opinions?