Transcript Final Presentation

Project duration – 1 year
AMC – Adaptive Mirror
Controller
Project supervised by:
Mony Orbach
Project performed by:
Koren Erez, Turgeman Tomer
Introduction


The project is a collaboration between the
Physic’s Adaptive Optics Lab and HS DSL.
Developing a system that controls adaptive
mirrors, by changing the voltage of their
capacitors (up to 124 capacitors).
The Optical System
Signals & Rates
Input:

A serial signal from the computer through a
USB.
Output:

124 outlines of analog signal (0-295V).
Rate:

The system will update all 124 outputs in
1mSec.
External Flow Chart
USB
Optical Device
AMC
Adaptive Mirror
Internal Flow Chart
AMC
MMC
USB
USB Interface
8 Bit
FPGA
12 Bit
D/A
Amp. Amp. Amp. Amp.
Adaptive Mirror
The State
Machine (SM)

Implemented as FSM within the FPGA.

Main tasks:
– Data flow controlling.
– High Voltage Amplifiers power up/down
sequence Controlling.
– Carrying out a self test.
– FPGA-PC communication through the USB
module.

Including a Watch Dog Timer (WDT) feature
for a PC-FPGA synchronization.
The State
Machine (SM)
Power on AMC
+ USB cable
connection!
System
DLP,
FPGA
Power
Up
DLP
ready!
HVAmp
Power
Up
Power
Down
Power off AMC +
USB cable
disconnection!
HVAmps are
powered on
HVAmp
Power
Down
Self Test
Byte!
Self
test
MAIN
Shutdown Byte!
EOT = End Of Transmission
WDTR = Watch Dog Timer Reset
DLP = USB Module
HVAmp = High Voltage Amplifier
The Control Bytes are marks in green
OK/Error
Massage
Status
Byte!
RUN
Byte!
RUN
EOT
All capacitors
were charged/
WDTR!
DLP to
PC
Transmi
t
Testing The System


The testing process composed of separate
checks for all of the system modules.
The modules are:
–
–
–
The MMC card (HW & FW)
The amplification cards
The Wire-Wrap, containing:





Bus-Exchanger
Latches
Switches and Relay
Quad D/A
Comparator
The MMC card (HW & FW)

Checking the HW:
– Programming the FPGA with a simple program
and sampling the FPGA’s pins and the
transceiver’s inputs/outputs
– Sampling the regulators

Checking the FW:
– Comprehensive Test Bench was created in order
to simulate the PC communication
– All the SM states were examined
The amplification cards

Two additional cards were made for this
test. This cards contained:
– Voltage switching capabilities for the power
up/down sequence
– DIP Switch controlled address and EN signals
– Analog signal, connected to a signal generator.

A 5pF capacitor was connected to the
output of the tested amplifier, in order to
resemble the mirror capacitors.
The Wire-Wrap


We added two headers on the cards
that were used to check the
amplification capability
This headers simulated logic inputs
and control lines that could be
switched in order to examine the
WW’s components
AMC SW Interface

C++ functions were written in order to
communicate with the AMC:
What we’ve learn

HW practice:
–
–
–
–

Reading datasheets
Component selection
Wire Wrap
Modular testing
FPGA Development flow:
– HDL Designer development environment
– Logic & timing simulation

Multidiscipline work:
– Customer: Physic’s Adaptive Optics Lab
– Semi contractor: Supertex
– Soldering & Assembly with Bruria
Thanks for your support!
Erez & Tomer
HVAmp Power Up/Down



Improper power up/down sequence can damage
the HVAmps (High Voltage Amplifiers).
Power up sequence:
Vpp(300V)Vnn(-5.5V)Vdd(6.5V)
Power down sequence:
Vdd(6.5V) Vnn(-5.5V)Vpp(300V)
HVAmp Power Up/Down




In order to control the Power up/down sequence, The
system includes Latch, Switches & Relay.
The switches and the relay responsible on the physical
connection between the power supplies and the
HVAmps.
The power up/down control lines toggle the switches for
the appropriate sequence.
The Latch locks the state of the switches when the
system finished power up. This allows a reduction of
control lines.
HVAmp Power Up/Down
HVAmp Power Supply
Power Up/Down Unit
Switches
Transceiver
Transceiver
HVAmp
Latch
Bus
Computer
Relay
Exchange
DLP
(USB)
Transceiver
HVAmp
Cyclone
FPGA
Adaptive
Mirror
Quad
HVAmp
Voltage
Output
Comparator
'1'
CLK
EPCS
Reset
D/A
HVAmp
HVAmp Power Up/Down
HVAmp Power Supply
Switches
Transceiver
HVAmp
Latch
Bus
Exchange
Relay
HVAmp
Cyclone
FPGA
Adaptive
Mirror
HVAmp
HVAmp
The State Machine- MAIN
State

The FPGA waits for a Control Sequence from the PC.

The Control Sequence composed of 3 bytes:
0xFF
0x00
Control Byte
Flag

According to The Control Byte the FPGA shifts to the
next state:
• RUN Byte - updating all 124 outputs with the data received from
the PC.
• Self Test Byte - initiating a self test cycle.
• Shutdown Byte - Power Down the High Voltage Amplifiers.
• Status Byte - Status reporting to the PC.
Self Test

The self test gives indication that:
– All components were powered up.
– All components are working properly.
– Proper data flow.

The FPGA sends the test’s result to the
PC by the DLP module.
Self Test
HVAmp Power Supply
Switches
Transceiver
Transceiver
HVAmp
Latch
Bus
Computer
Relay
Exchange
DLP
(USB)
Transceiver
HVAmp
Cyclone
FPGA
Adaptive
Mirror
Quad
HVAmp
Voltage
Output
Comparator
'1'
CLK
EPCS
Reset
D/A
HVAmp
Self Test
Transceiver
HVAmp
Transceiver
Bus
Computer
Exchange
DLP
(USB)
Transceiver
HVAmp
Cyclone
FPGA
Adaptive
Mirror
Quad
HVAmp
Voltage
Output
Comparator
'1'
D/A
HVAmp
Self Test –
Comparators Scheme