Transcript VTS99 Paper Presentation

Floating Point Types for Synthesis
Alex N. D. Zamfirescu
Alternative System Concepts, Inc.
VIUF October, 2000
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Copyright 2000 Alternative System Concepts, Inc.
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Presentation Outline
 Introduction
 Floating point numbers
 VHDL floating point problems
 Solutions

IEEE 754 model kind VHDL FP type

Support Java virtual machine FP

Arbitrary FP VHDL types
 How to proceed
 Verification speed
 Conclusion
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Introduction (1 of 2)
 Computers are integer machines, real numbers are
represented using complex codes
 The “IEEE Floating-Point Standard Format” is described in
IEEE 754 Std. (best explained in [1])
 Term “floating-point”) (FP means that there is no fixed
number of digits before and after the decimal point
(decimal point can float)
 For specific algorithms more then necessary
computations are performed. Many extra operations have
little or no effect
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Reality
 FP operations are area and power expensive optimizations are required
 Smaller cores do not provide FP support today
 Many optimizations are not feasible with a strict standard
format (fixed size fields)
 High precision machines are hard to design using just
what the standard IEEE 754 provides (simple, double and
extended precision)
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Floating Point Numbers (1 of 2)
 General form of FP number is
x = s * M * B ^p
 Representations restrict ranges of mantissa M and
exponent p, and chose base B
 After computations some bits of the mantissa are
not stored

chopped (completely discarded)

rounded

to infinity
 to zero
 random
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Floating Point Numbers (2 of 2)
 Storing 1.11010101 with 3 places after point gives

1.110 when chopping

1.111 while rounding
 First bit after normalization can be hidden (since it is
known to be always one)
 IEEE std uses B = 2 works from a number written as
x = s*1.ffff...ff(binary)*2^p
where mantissa is a binary number whose leading 1 will be
“hidden when the number is stored
 Other issues: NAN, and zero representation and
exception handling (underflow, overflow)
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VHDL FP Problems
 Two kinds of FP formats are considered

machine kind - formats used by the machines implementing VHDL

model kind - formats used in the model
 First Problem: Either the machine and the model formats
are the same or the model format is not easily
recognizable by synthesis tools
 Second Problem: Operations with proprietary model kind
FP formats are not fast enough to enable execution and
evaluation of different choices
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Solution 1: Bit Access to an IEEE 754
Format
 Support IEEE 754 for specific standard bit (std_logic)
vector types
 Make convention for bit sign
 Specify mantissa size via attribute or convention for
specific bit (i.e. bit zero)
exponent
-m
mantissa
0
n
 CONS:

need smaller less expensive (area and/or power) formats

design of future high precision machines is not addressed

choices needed for zero, NANs and exceptions are arbitrary
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Solution 2: Support for Java Virtual
Machine FP Type
 Java Virtual Machine support for FP is standard
 Many hand held devices currently designed have to
support Java
 An enhanced solution 1 where all choices for what IEEE
754 left open follow most popular alternatives
 Same first two CONS as Solution 1
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Solution 3: Arbitrary FP VHDL Types
The Challenges
(1 of 3)
 A relatively complex set of properties has to be specified
to characterize the format
 Operators have to be specified for all possible
combinations of choices
 Lose synthesis choices have to be left in handling some
exceptions
 Format properties should either be associated with the
model or be automatically extracted form available library
data
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Solution 3: Arbitrary FP VHDL Types
Describing the type
(2 of 3)
 VHDL attributes do not provide for

verification that set is complete and values are in a permitted

outside VHDL format (challenge number 4)
 Solution: Enter the FP format properties via XML

as a string value of a VHDL attribute,

directly insertion in VHDL (after VHDL language modifications that
would permit it)
 XML enables checking of any rules that FP formats
properties have to comply with
 Same XML file could be extracted from libraries and then
read by the synthesis and verification tools
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Solution 3: Arbitrary FP VHDL Types
Describing operators
(3 of 3)
 The second challenge could be addressed via the
introduction of a minimal set of new VHDL type system
features
 The following features will help reduce the difficulty of
implementing the operator functionality for all possible
choices

“Protected” polymorphism (language can stay strong typed only
specific packages get the feature)

Variant records

C++ like templates. In fact
(such features are also required in describing configurable
hardware)
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How to Proceed (1 of 3)
Tasks listed by solution
 Solution 1 and 2:

agreement on the definition of the type

implementation of a library of operators
 Solution 3.

The design of a DTD (document template definition) for the XML
content (FP type properties like sizes, normalization, exponent
encoding, base value, truncation scheme, hidden bit, exception
handling, defaults, etc.)

A choice for the XML insertion mechanism into VHDL

The extension/import of ADA-95 machine kind FP attributes to the
model kind VHDL FP types

The implementation of a library of operators after extending the
language to support templates.
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How to Proceed (2 of 3)
Standard development implications
 Start as enhancements of IEEE 1076.3 or under IEEE
project 1076.6
 XML approach to the type descriptor is sharable (with
Verilog, and system level efforts)
 Therefore, the type descriptor belongs to a set of
standards that are shared by more languages
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How to Proceed (3 of 3)
Semantics standards and their inheritors
Common HDL definitions (i.e.design hierarchy, event)
XML DTD or Schema
What is the content of
a FP type descriptor
FP Operator
semantic
Future VHDL
VHDL FP library implementation
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Future Verilog
Verilog FP library implementation
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Verification Speed
Acceleration feasible via:
1. Resident machine FP
- when all model FP parameter ranges are
included in the IEEE 754 permitted ranges
2. Byte and word manipulations in C or native code
3. Configurable co-processor
- programmable at elaboration
- connected over the bus
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Conclusion
 Distinction between machine and model kind FP types
reveals VHDL FP problems
 Supporting IEEE 754 Java VM like FP types is the best
simple solution
 An XML based FP descriptor could lead to unified support
of FP types in VHDL and Verilog
 Role for semantic standards in HDL was identified
 A new set of optimizations for area and low power become
feasible through the users’ choice of FP formats
 Meaning (semantics) inheritance is more important then
model properties inheritance (for the HDL progress)
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